參數(shù)資料
型號： (Z)PSD813F2
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲器，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位和256K位閃速存儲器，16K的位的SRAM）
文件頁數(shù)： 6/32頁
文件大?。?/td> 297K
代理商： (Z)PSD813F2
PSD813FH - 80C31 Design Example …Application Note
052
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
6
Figure 3 - Schematic
System Memory Map
The system memory map is shown in Figures 4 and 5. The labels FSx and CSBOOTx are the
names of internal memory blocks within the MCM device. FSx = blocks of main FLASH (16
Kbytes each), CSBOOTx = blocks of OTP boot ROM (8 Kbytes each).
There are two fundamental modes of operation, one is boot/download mode, and the other is
normal operation. Figure 4 represents the memory map at power on (boot). The system will boot
up from MCM PSD OTP boot ROM, then facilitate a download of the main FLASH memory (if
needed) using the 8031 UART. At this point, all of main FLASH memory is combined in 8031
"data" and "program" space so it can be treated as data. Next, Figure 5 represents the memory
map after the FLASH has been programmed and/or validated. The boot ROM that the system
booted from during power up is now replaced with FLASH memory that contains application
vectors and code. The transition between the two maps is under control of the 8031 by setting a
"SWAP" bit inside the PSD. After the "SWAP" bit is set, all of main FLASH memory resides in
8031 "program" space only, not "data" space.
In this design, paging is used because the system contains more memory than the 8031 can
address linearly. The PSD6XX die in the MCM facilitates paging by using a page register, which
is accessible by the 8031. Because paging is used, an area of common memory is needed for
firmware routines that must be accessible regardless of what page the MCU is executing from.
This common area resides in the lower half of each memory page (Figure 5) in program space
and should contain routines that handle initialization, interrupts, implement page switching, and
drive physical devices. It is also important to keep critical data space items available at all times.
For example, in this design, the PSD control registers, I/O, and system SRAM for the stack and
global variables are available on any memory page (Figures 4 and 5, System RAM & I/O).
Figure 4 - Memory Map - Boot/Download Mode (SWAP bit = 0)
FFFF
0000
4000
8000
C000
1000
FS1
FS1
FS1
FS1
FS2
FS3
FS4
FS5
FS6
FS0
PAGE 0
PAGE 1
PAGE 2
PAGE 3
COMMON
MEMORY
ACROSS ALL
DATA PAGES
SYSTEM RAM & I/O
CSBOOT1
FS7
<<< FLASH KEYHOLE 5555
<<<FLASH KEYHOLE AAAA
(2AAA with a15f grounded)
CSBOOT0
FFFF
0000
4000
8000
C000
2000
PAGE X
NOTHING MAPPED
SYSTEM RAM & I/O
SYSTEM RAM & I/O
SYSTEM RAM & I/O
NOTHING MAPPED
NOTHING MAPPED
NOTHING MAPPED
Execute
from
here
DATA SPACE (RD\, WR\)
PROGRAM SPACE (PSEN\)
IALL OF FLASH
ALSO. HOWEVER,
USED AS DATA
DURING DOWNLOAD.
NOTHING MAPPED
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD813F2-12JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-12UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15J 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-15U 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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