參數(shù)資料
型號(hào)： (Z)PSD813F2
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲(chǔ)器，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬(wàn)位和256K位閃速存儲(chǔ)器，16K的位的SRAM）
文件頁(yè)數(shù)： 12/32頁(yè)
文件大?。?/td> 297K
代理商： (Z)PSD813F2
PSD813FH - 80C31 Design Example …Application Note
052
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
12
segment has its own chip select equation. For this design, only two segments (16 Kbytes total)
are used to maximize the amount of main FLASH memory available to the 8031. This trade-off
will not affect the monolithic FLASH PSDs because they have more flexible memory mapping
capability than the MCM FLASH PSD devices. Here are the PSDabel equations:
csboot0= ((address >= ^h0000) & (address <= ^h1FFF) & (page == X) & !swap);
csboot1= ((address >= ^h2000) & (address <= ^h3FFF) & (page == X) & !swap);
When this MCM design is ported to a monolithic FLASH PSD device, the MCM OTP boot ROM
shall become ISP Non-Volatile Memory instead. The monolithic PSD813F1 device will offer 32
Kbytes of EEPROM, the PSD813F2/F4 will offer 32 Kbytes of FLASH. This allows updates of
boot code from the host. ISP of boot memory will be covered in separate applications notes for
the monolithic PSD devices. Also, refer to the section covering Conversion Issues at the end of
this document.
Accessing the PSD SRAM
Although the SRAM in this MCM device is 512 bytes, the monolithic FLASH PSDs (except
PSD813F4/F5) have 2 Kbytes, thus 2 Kbytes of address space are decoded here. The decoded
SRAM space begins at the address just after the 8031 internal RAM ends and is active on any
page.
rs0_node = (address >= ^h0100) & (address <= ^h08FF) & (page == X);
rs0 = rs0_node;
Note: This address range involves a feedback term in the rs0 equation. Due to the internal
architecture of the MCM, the solution to rs0 has to include a node tied to a port pin. This
node, rs0_node, is declared on pin pb7 of Port B. When this MCM design is converted to a
monolithic FLASH PSD, this intermediate node will not be needed. rs0 can be used
directly, and pb7 will be available for I/O.
Accessing I/O
Here are PSDabel equations related to I/O for this design. All I/O is active on any memory page.
PSD internal control space (256 bytes).
csiop
= (address >= ^h0900) & (address <= ^h09FF) & (page == X);
Generic external chip selects. These can be used for peripherals or memory (LCD module, ADC,
DAC, UART, CAN, more SRAM, etc).
cs_dev0 = (address >= ^h0A00) & (address <= ^h0AFF) & (page == X);
" 256 bytes
cs_dev1 = (address >= ^h0B00) & (address <= ^h0BFF) & (page == X);
" 256 bytes
cs_dev2 = (address >= ^h0C00) & (address <= ^h0DFF) & (page == X);
" 256 bytes
cs_dev3 = (address >= ^h0E00) & (address <= ^h0FFF) & (page == X);
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD813F2-12JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-12UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15J 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
ZPSD813F2-15U 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
ZPSD813F2-15UI 制造商:WSI 功能描述: 制造商:WSI 功能描述:1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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