參數資料
型號: W9712G8JB-3
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: DDR DRAM, PBGA60
封裝: 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60
文件頁數: 9/86頁
文件大小: 1039K
代理商: W9712G8JB-3
W9712G8JB
Publication Release Date: Oct. 12, 2010
- 17 -
Revision A01
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as
shown in Figure 7. For input data pattern for adjustment, DT0 - DT3 is a fixed order and is not affected
by burst type (i.e., sequential or interleave).
OCD adjust mode
OCD calibration mode exit
WR
WL
DQS
tDS tDH
DT0
EMRS(1)
NOP
CLK
DQS_in
CMD
DQ_in
DM
NOP
EMRS
NOP
EMRS
CLK
DT1
DT2
DT3
Figure 7 – OCD Adjust Mode
7.2.3.3
Drive Mode
Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver
impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all
output drivers are turned-off tOIT after “OCD calibration mode exit” command as shown in Figure 8.
Enter Drive mode
OCD calibration mode exit
EMRS
NOP
CLK
DQS
CMD
DQ
tOIT
DQs high for Drive (1)
DQs low for Drive (0)
DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0)
CLK
HI-Z
Figure 8 – OCD Drive Mode
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