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參數(shù)資料
| 型號： | W9712G8JB-3 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60 |
| 文件頁數(shù)： | 29/86頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | W9712G8JB-3 |
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W9712G8JB
Publication Release Date: Oct. 12, 2010
- 35 -
Revision A01
Function Truth Table, continued
CURRENT
STATE
CS
RAS
CAS
WE
ADDRESS
COMMAND
ACTION
NOTES
Write
Recovering
H
X
DSL
NOP-> Bank active after tWR
L
H
X
NOP
NOP-> Bank active after tWR
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
1
L
H
L
BA, CA, A10
WRIT/WRITA
New write
L
H
BA, RA
ACT
ILLEGAL
1
L
H
L
BA, A10
PRE/PREA
ILLEGAL
1
L
H
X
AREF/SELF
ILLEGAL
L
Op-Code
MRS/EMRS
ILLEGAL
Write
Recovering
with Auto-
precharge
H
X
DSL
NOP-> Precharge after tWR
L
H
X
NOP
NOP-> Precharge after tWR
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
1
L
H
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
1
L
H
BA, RA
ACT
ILLEGAL
1
L
H
L
BA, A10
PRE/PREA
ILLEGAL
1
L
H
X
AREF/SELF
ILLEGAL
L
Op-Code
MRS/EMRS
ILLEGAL
Refreshing
H
X
DSL
NOP-> Idle after tRC
L
H
X
NOP
NOP-> Idle after tRC
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
L
H
BA, RA
ACT
ILLEGAL
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
H
X
AREF/SELF
ILLEGAL
L
Op-Code
MRS/EMRS
ILLEGAL
Mode
Register
Accessing
H
X
DSL
NOP-> Idle after tMRD
L
H
X
NOP
NOP-> Idle after tMRD
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
L
H
BA, RA
ACT
ILLEGAL
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
H
X
AREF/SELF
ILLEGAL
L
Op-Code
MRS/EMRS
ILLEGAL
Notes:
1. This command may be issued for other banks, depending on the state of the banks.
2. All banks must be in "IDLE".
3. Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8. Burst read/write can
only be interrupted by another read/write with 4 bit burst boundary. Any other case of read/write interrupt is not allowed.
Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W971GG6IB-25 | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| W9751G6JB-25A | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| W9751G8JB-18 | DDR DRAM, PBGA84 |
| W9812G21H-6I | 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| W9812G21H-6C | 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W971GG6JB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM |
| W971GG6JB-18 | 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS |
| W971GG6JB-25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA |
| W971GG6JB25I | 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
| W971GG6JB-25I | 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY |
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