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參數(shù)資料
| 型號： | W9712G8JB-3 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60 |
| 文件頁數(shù)： | 44/86頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | W9712G8JB-3 |
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W9712G8JB
Publication Release Date: Oct. 12, 2010
- 49 -
Revision A01
DQS
tDS(base) tDH(base)
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
tDS(ref)
tDH(ref)
tDS(ref)
tDH(ref)
Logic levels
VREF levels
Figure 19
– Differential input waveform timing – tDS and tDH
18. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active
power down exit timing. tXARDS is expected to be used for slow active power down exit timing.
19. AL = Additive Latency.
20. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND, which is interpreted differently per speed bin.
For DDR2-667/800/1066, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual
input clock edges.
21. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD.
For DDR2-667/800: This is interpreted differently per speed bin. If tCK(avg) = 3 nS is assumed, tAOFD is 1.5 nS (=
0.5 x 3 nS) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by
counting the actual input clock edges.
For DDR2-1066: This is interpreted as 0.5 x tCK(avg) [nS] after the second trailing clock edge counting from the
clock edge that registered a first ODT LOW and by counting the actual input clock edges. tAOFD is 0.9375 [nS] (=
0.5 x 1.875 [nS]) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW
and by counting the actual input clock edges.
22. The clock frequency is allowed to change during Self Refresh mode or precharge power-down mode. In case of clock
frequency change during precharge power-down, a specific procedure is required as described in section 7.10.
23. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM /
tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
Examples:
The device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are
met. This means: For DDR2-667 5-5-5, of which tRP = 15nS, the device will support tnRP = RU{tRP / tCK(avg)} = 5,
i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+5
is valid even if (Tm+5 - Tm) is less than 15nS due to input clock jitter. For DDR2-1066 7-7-7, of which tRP = 13.125
nS, the device will support tnRP = RU{tRP / tCK(avg)} = 7, i.e. as long as the input clock jitter specifications are met,
Precharge command at Tm and Active command at Tm+7 is valid even if (Tm+7 - Tm) is less than 13.125 nS due to
input clock jitter.
24. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [pS] / tCK(avg) [pS] }, where WR is the value programmed in the
mode register set and RU stands for round up.
Example:
For DDR2-1066 7-7-7 at tCK(avg) = 1.875 nS with WR programmed to 8 nCK, tDAL = 8 + RU{13.125 nS / 1.875
nS} [nCK] = 8 + 7 [nCK] = 15 [nCK].
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W971GG6IB-25 | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| W9751G6JB-25A | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| W9751G8JB-18 | DDR DRAM, PBGA84 |
| W9812G21H-6I | 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| W9812G21H-6C | 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W971GG6JB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM |
| W971GG6JB-18 | 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS |
| W971GG6JB-25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA |
| W971GG6JB25I | 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
| W971GG6JB-25I | 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY |
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