參數(shù)資料
型號(hào)： W9712G8JB-3
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： DDR DRAM, PBGA60
封裝： 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60
文件頁(yè)數(shù)： 31/86頁(yè)
文件大?。?/td> 1039K
代理商： W9712G8JB-3
W9712G8JB
Publication Release Date: Oct. 12, 2010
- 37 -
Revision A01
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
NOTES
Voltage on VDD pin relative to VSS
VDD
-1.0 ~ 2.3
V
1, 2
Voltage on VDDQ pin relative to VSS
VDDQ
-0.5 ~ 2.3
V
1, 2
Voltage on VDDL pin relative to VSS
VDDL
-0.5 ~ 2.3
V
1, 2
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 2.3
V
1, 2
Storage Temperature
TSTG
-55 ~ 100
°C
1, 2, 3
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. When VDD and VDDQ and VDDL are less than 500mV; VREF may be equal to or less than 300mV.
3. Storage temperature is the case surface temperature on the center/top side of the DRAM.
9.2 Operating Temperature Condition
PARAMETER
SYMBOL
RATING
UNIT
NOTES
Operating Temperature
TOPR
0 ~ 85
°C
1, 2, 3
Notes:
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting 0 ~ 85°C with full AC and DC specifications.
3. Supporting 0 ~ 85 °C and being able to extend to 95 °C with doubling Auto Refresh commands in frequency to a 32 mS
period ( tREFI = 7.8 S), the High Temperature Self Refresh has to be enabled by setting EMR (2) bit A7 to 1. When the High
Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%.
9.3 Recommended DC Operating Conditions
(0°C ≤ TCASE ≤ 85°C for -18/-25/-3, VDD, VDDQ = 1.8V ± 0.1V)
SYM.
PARAMETER
MIN.
TYP.
MAX.
UNIT
NOTES
VDD
Supply Voltage
1.7
1.8
1.9
V
1
VDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
5
VDDQ
Supply Voltage for Output
1.7
1.8
1.9
V
1, 5
VREF
Input Reference Voltage
0.49 x VDDQ
0.5 x VDDQ
0.51 x VDDQ
V
2, 3
VTT
Termination Voltage (System)
VREF - 0.04
VREF
VREF + 0.04
V
4
Notes:
1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ
must than or equal to VDD.
2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF
is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
3. Peak to peak AC noise on VREF may not exceed
±2 % VREF(dc).
4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and device must track VREF of receiving device.
5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
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