參數(shù)資料
型號(hào): W9712G8JB-3
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: DDR DRAM, PBGA60
封裝: 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60
文件頁數(shù): 33/86頁
文件大小: 1039K
代理商: W9712G8JB-3
W9712G8JB
Publication Release Date: Oct. 12, 2010
- 39 -
Revision A01
9.7
Capacitance
SYM.
PARAMETER
MIN.
MAX.
UNIT
CCK
Input Capacitance , CLK and CLK
1.0
2.0
pF
CDCK
Input Capacitance delta , CLK and CLK
0.25
pF
CI
input Capacitance, all other input-only pins
1.0
2.0
pF
CDI
Input Capacitance delta, all other input-only pins
0.25
pF
CIO
Input/output Capacitance, DQ, DM,
DQS, DQS ,RDQS, RDQS
2.5
3.5
pF
CDIO
Input/output Capacitance delta, DQ, DM,
DQS, DQS ,RDQS, RDQS
0.5
pF
9.8
Leakage and Output Buffer Characteristics
SYM.
PARAMETER
MIN.
MAX.
UNIT
NOTES
IIL
Input Leakage Current
(0V
VIN VDD)
-2
2
A
1
IOL
Output Leakage Current
(Output disabled, 0V
VOUT VDDQ)
-5
5
A
2
VOH
Minimum Required Output Pull-up
VTT + 0.603
V
VOL
Maximum Required Output Pull-down
VTT - 0.603
V
IOH(dc)
Output Minimum Source DC Current
-13.4
mA
3, 5
IOL(dc)
Output Minimum Sink DC Current
13.4
mA
4, 5
Notes:
1. All other pins not under test = 0 V.
2. DQ, DQS, DQS , RDQS, RDQS are disabled and ODT is turned off.
3. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT - VDDQ)/IOH must be less than 21 for values of VOUT between VDDQ and VDDQ -
0.28V.
4. VDDQ = 1.7 V; VOUT = 0.28V. VOUT/IOL must be less than 21 for values of VOUT between 0 V and 0.28V.
5. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 3 and 4. They are used to test drive current
capability to ensure VIHmin plus a noise margin and VILmax minus a noise margin are delivered to an SSTL_18 receiver.
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