參數(shù)資料
型號(hào)： W9712G8JB-3
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： DDR DRAM, PBGA60
封裝： 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60
文件頁(yè)數(shù)： 34/86頁(yè)
文件大小： 1039K
代理商： W9712G8JB-3
W9712G8JB
Publication Release Date: Oct. 12, 2010
- 4 -
Revision A01
1. GENERAL DESCRIPTION
The W9712G8JB is a 128M bits DDR2 SDRAM, organized as 4,194,304 words
× 4 banks × 8 bits.
This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general
applications. W9712G8JB is sorted into the following speed grades: -18, -25 and -3. The -18 is
compliant to the DDR2-1066 (7-7-7) specification. The -25 is compliant to the DDR2-800 (5-5-5) or
DDR2-800 (6-6-6) specification. The -3 is compliant to the DDR2-667 (5-5-5) specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.8 V
± 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data.
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 60 Ball (8X12.5 mm
2), using Lead free materials with RoHS compliant
相關(guān)PDF資料
PDF描述
W971GG6IB-25 32M X 16 DDR DRAM, 0.4 ns, PBGA84
W9751G6JB-25A 32M X 16 DDR DRAM, 0.4 ns, PBGA84
W9751G8JB-18 DDR DRAM, PBGA84
W9812G21H-6I 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86
W9812G21H-6C 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W971GG6JB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM
W971GG6JB-18 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS
W971GG6JB-25 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA
W971GG6JB25I 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR
W971GG6JB-25I 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*