參數(shù)資料
型號(hào)： W9712G8JB-3
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： DDR DRAM, PBGA60
封裝： 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60
文件頁(yè)數(shù)： 46/86頁(yè)
文件大?。?/td> 1039K
代理商： W9712G8JB-3
W9712G8JB
Publication Release Date: Oct. 12, 2010
- 50 -
Revision A01
25. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667, DDR2-800 and DDR2-1066.
Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation.
Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Examples:
For DDR2-667/800: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm+2, even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min.
For DDR2-1066: tXP = 3 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm+3, even if (Tm+3 - Tm) is 3 x tCK(avg) + tERR(3per),min.
26. These parameters are measured from a command/address signal (CKE, CS , RAS , CAS , WE , ODT, BA0, A0, A1, etc.)
transition edge to its respective clock signal (CLK/ CLK ) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the
command/address. That is, these parameters should be met whether clock jitter is present or not.
27. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can
be executed.
28. These parameters are measured from a data strobe signal (DQS, DQS , RDQS, RDQS ) crossing to its respective clock
signal (CLK/ CLK ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc),
etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is
present or not.
29. These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe
signal (DQS, DQS , RDQS, RDQS ) crossing.
相關(guān)PDF資料
PDF描述
W971GG6IB-25 32M X 16 DDR DRAM, 0.4 ns, PBGA84
W9751G6JB-25A 32M X 16 DDR DRAM, 0.4 ns, PBGA84
W9751G8JB-18 DDR DRAM, PBGA84
W9812G21H-6I 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86
W9812G21H-6C 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W971GG6JB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM
W971GG6JB-18 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS
W971GG6JB-25 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA
W971GG6JB25I 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR
W971GG6JB-25I 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY
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