參數(shù)資料
型號(hào)： W9712G8JB-3
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： DDR DRAM, PBGA60
封裝： 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60
文件頁(yè)數(shù)： 36/86頁(yè)
文件大?。?/td> 1039K
代理商： W9712G8JB-3
W9712G8JB
Publication Release Date: Oct. 12, 2010
- 41 -
Revision A01
IDD4R
Operating Burst Read Current
All banks open, Continuous burst reads, IOUT = 0 mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
120
95
90
mA
1,2,3,4,5,
6
IDD4W
Operating Burst Write Current
All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
135
120
115
mA
1,2,3,4,5,
6
IDD5B
Burst Refresh Current
tCK = tCK(IDD);
Refresh command every tRFC(IDD) interval;
CKE is HIGH, CS is HIGH between valid commands;
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
90
80
mA
1,2,3,4,5,
6
IDD6
Self Refresh Current
CKE
≤ 0.2 V, external clock off, CLK and CLK at 0 V;
Other control and address inputs are FLOATING;
Data bus inputs are FLOATING.
6
mA
1,2,3,4,5,
6
IDD7
Operating Bank Interleave Read Current
All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD =
tRCD(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during deselects;
Data Bus inputs are SWITCHING.
170
140
130
mA
1,2,3,4,5,
6
Notes:
1. VDD = 1.8 V
± 0.1V; VDDQ = 1.8 V± 0.1V.
2. IDD specifications are tested after the device is properly initialized.
3. Input slew rate is specified by AC Parametric Test Condition.
4. IDD parameters are specified with ODT disabled.
5. Data Bus consists of DQ, DM, DQS, DQS , RDQS, RDQS .
6. Definitions for IDD
LOW = Vin
≤ VIL (ac) (max)
HIGH = Vin
≥ VIH (ac) (min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at VREF = VDDQ/2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
相關(guān)PDF資料
PDF描述
W971GG6IB-25 32M X 16 DDR DRAM, 0.4 ns, PBGA84
W9751G6JB-25A 32M X 16 DDR DRAM, 0.4 ns, PBGA84
W9751G8JB-18 DDR DRAM, PBGA84
W9812G21H-6I 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86
W9812G21H-6C 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W971GG6JB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM
W971GG6JB-18 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS
W971GG6JB-25 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA
W971GG6JB25I 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR
W971GG6JB-25I 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*