參數(shù)資料
型號: SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 72/175頁
文件大?。?/td> 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
72 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
FIDT: detected field frequency has changed (50 Hz
60 Hz).
RDCAP: ready for capture (true
DCSTD[1:0]: detected color standard has changed or color lost.
COPRO, COLSTR and TYPE3: various levels of copy protection have changed.
9.4.1.3
VBI data slicer
VPSV: VPS identification found or lost.
PPV: PALplus identification found or lost.
CCV: Closed caption identification found or lost.
9.4.1.4
Scaler
ERROF: scaler output formatting error detected.
9.4.2
Status reading conditions
The status information read after an interrupt will always be the LATEST state, that means
the status will not be ‘frozen’ when an interrupt is being generated. Therefore, if there is a
long time between interrupt generation and status reading, the original trigger condition
might have been overridden by the present state.
9.4.3
Erasing conditions
The status flags are grouped into four 8-bit registers.
The interrupt flag will only be cleared on a read access to the status register in which the
signal is located which caused the interrupt. This implies that it is sufficient to clear the
interrupt by reading only those registers which have been enabled by their corresponding
masks.
Priority: If a new trigger condition occurs at the SAME time (clock) on which a status is
being read, the flag will NOT be cleared.
9.5 Video expansion port (X port)
The expansion port is intended for transporting video streams image data from other
digital video circuits such as MPEG encoder/decoder and video phone codec, to the
image port (I port).
The expansion port consists of two groups of signals/pins:
8-bit data, I/O, regularly components video Y-C
B
-C
R
4 : 2 : 2, i.e. C
B
-Y-C
R
-Y, byte
serial, exceptionally raw video samples (e.g. ADC test); in input mode the data bus
can be extended to 16-bit by pins HPD7 to HPD0
Clock, synchronization and auxiliary signals, accompanying the data stream, I/O
As output, these are direct copies of the decoder signals.
The data transfers through the expansion port represent a single D1 port, with half duplex
mode. The SAV and EAV codes may be inserted optionally for data input (controlled by
bit XCODE[92h[3]]). The input/output direction is switched for complete fields only.
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