參數(shù)資料
型號: SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 136/175頁
文件大小: 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
136 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
For trigger condition: STRC[1:0] 90h[1:0] = 00; YO + YS > (number of input lines per field
2), will result in field dropping. Other trigger
conditions: YO > (number of input lines per field
2), will result in field dropping.
[1]
For trigger condition: STRC[1:0] 90h[1:0] = 00; YO + YS > (number of input lines per field
2), will result in field dropping. Other trigger
conditions: YS > (number of input lines per field
2), will result in field dropping.
10.7.8
Subaddresses 9Ch to 9Fh
[1]
Reference for counting are luminance samples.
[2]
If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated.
Table 119. Vertical input window start; register set A [98h[7:0]; 99h[3:0]] and B [C8h[7:0]; C9h[3:0]]
Vertical input acquisition window
definition offset in Y (vertical)
direction
[1]
B [C9h[3:0]]
YO11 YO10 YO9
Line offset = 0
0
0
Line offset = 1
0
0
Maximum line offset = 4095
1
1
Control bits
A [99h[3:0]] and
A [98h[7:0]] and B [C8h[7:0]]
YO8
0
0
1
YO7
0
0
1
YO6
0
0
1
YO5
0
0
1
YO4
0
0
1
YO3
0
0
1
YO2
0
0
1
YO1
0
0
1
YO0
0
1
1
0
0
1
Table 120. Vertical input window length; register set A [9Ah[7:0]; 9Bh[3:0]] and B [CAh[7:0]; CBh[3:0]]
Vertical input acquisition window
definition input window length in
Y (vertical) direction
[1]
B [CBh[3:0]]
YS11 YS10 YS9
No input lines
0
0
1 input line
0
0
Maximum possible number of input
lines = 4095
Control bits
A [9Bh[3:0]] and
A [9Ah[7:0]] and B [CAh[7:0]]
YS8
0
0
1
YS7
0
0
1
YS6
0
0
1
YS5
0
0
1
YS4
0
0
1
YS3
0
0
1
YS2
0
0
1
YS1
0
0
1
YS0
0
1
1
0
0
1
1
1
Table 121. Horizontal output window length; register set A [9Ch[7:0]; 9Dh[3:0]] and B [CCh[7:0]; CDh[3:0]]
Horizontal output acquisition
window definition number of
desired output pixels in
X (horizontal) direction
[1]
XD11 XD10 XD9
No output
0
0
0
Odd lengths are allowed, but will be
filled up to even lengths
Maximum possible number of input
pixels = 4095
[2]
Control bits
A [9Dh[3:0]] and
B [CDh[3:0]]
A [9Ch[7:0]] and B [CCh[7:0]]
XD8
0
0
XD7
0
0
XD6
0
0
XD5
0
0
XD4
0
0
XD3
0
0
XD2
0
0
XD1
0
0
XD0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
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