參數(shù)資料
型號: SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 119/175頁
文件大小: 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
119 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
10.2.28
Subaddress 1Fh
10.3 Programming register RGB/Y-P
B
-P
R
component input processing
10.3.1
Subaddress 23h
Table 66.
Bit
Status byte 2 video decoder; 1Fh[7:5] and 1Fh[3:0]; read only register
Description
I
2
C-bus
control bit
status bit for interlace
detection
Value
Function
D7
INTL
0
1
0
1
0
1
0
1
non-interlaced
interlaced
both loops locked
unlocked
50 Hz
60 Hz
not active
active
D6
status bit for horizontal and
vertical loop
HLVLN
D5
identification bit for detected
field frequency
FIDT
D3
Macrovision encoded color
stripe burst type 3 (4 line
version) detected
Macrovision encoded color
stripe burst detected
(any type)
copy protected source
detected according to
Macrovision version up
to 7.01
ready for capture (all internal
loops locked)
TYPE3
D2
COLSTR
0
1
not active
active
D1
COPRO
0
1
not active
active
D0
RDCAP
0
1
not active
active
Table 67.
Bit
D7
D6
Analog input control 5 (AICO5); 23h[7:4] and 23h[2:0]
Description
analog output select
AD port output enable
Symbol
AOSL2
ADPE
Value
see
Table 59
0
1
0
Function
AD port is set to 3-state
AD port is enabled
all ADCs are clocked by the internal generated
line-locked clock
all ADCs are clocked by the external input clock on
CLKEXT
clamping is dependent on HLNRS[03h[6]]
reference selection (input signal is pulled into ADC
range)
disabled
enabled (any slope on EXMCLR input will reset the
internal gain control loop)
see
Table 69
D5
ADC clock selector
EXCLK
1
D4
clamping/reference selection
for all ADCs
REFA
0
1
D2
enable external source switch
indicator input EXMCLR
EXMCE
0
1
D1
static gain control channel 2
sign bit
static gain control channel 1
sign bit
GAI48
D0
GAI38
see
Table 68
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