參數(shù)資料
型號(hào): SAF7118H
廠商: NXP Semiconductors N.V.
元件分類(lèi): 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁(yè)數(shù): 61/175頁(yè)
文件大?。?/td> 898K
代理商: SAF7118H
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SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
61 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
See errata information in
Section 19.6
.
8.6 Image port output formatter (subaddresses 84h to 87h)
The output interface consists of a FIFO for video and for sliced text data, an arbitration
circuit, which controls the mixed transfer of video and sliced text data over the I port and a
decoding and multiplexing unit, which generates the 8-bit or 16-bit wide output data
stream and the accompanied reference and supporting information.
The clock for the output interface can be derived from an internal clock, decoder,
expansion port, or an externally provided clock which is appropriate for e.g. VGA and
frame buffer. The clock can be up to 33 MHz. The scaler provides the following video
related timing reference events (signals), which are available on pins as defined by
subaddresses 84h and 85h:
Output field ID
Start and end of vertical active video range
Start and end of active video line
Data qualifier or gated clock
Actually activated programming page (if CONLH is used)
Threshold controlled FIFO filling flags (empty, full and filled)
Sliced data marker
The discontinuous data stream at the scaler output is accompanied by a data valid flag (or
data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the
I port data bus (including the HPD pins in 16-bit output mode) are marked with code 00h.
The output interface also arbitrates the transfer between scaled video data and sliced text
data over the I port output.
The bits VITX1 and VITX0 (subaddress 86h) are used to control the arbitration.
As a further operation the serialization of the internal 32-bit double words to 8-bit or
optional 16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV
for video data, ANC or SAV/EAV codes for sliced text data) are done here.
For handshake with the VGA controller, or other memory or bus interface circuitry,
programmable FIFO flags are provided; see
Section 8.6.2
.
1101
MOJI (Japanese)
[1]
5.7272
programmable
(A7h)
programmable
Japtext
1110
Japanese format switch
(L20/22)
no sliced data transmitted
(video data selected)
5
open
1111
5
none
disable
Table 15.
DT[3:0]
62h[3:0]
Data types supported by the data slicer block
…continued
Standard type
Data rate
(Mbit/s)
Framing Code
(FC)
FC window
Hamming
check
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SAF7129AH/V1,557 功能描述:視頻 IC 6 DAC VIDEO ENCODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel