參數(shù)資料
型號: SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 54/175頁
文件大?。?/td> 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
54 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
Resulting FIR function.
8.4.2.2
Horizontal fine scaling (variable phase delay filter; subaddresses A8h to AFh and
D8h to DFh)
The horizontal fine scaling (VPD) should operate at scaling ratios between
1
2
and 2
(0.8 and 1.6), but can also be used for direct scaling in the range from
1
7.999
to
(theoretical) zoom 3.5 (restriction due to the internal data path architecture), without
prescaler.
In combination with the prescaler a compromise between sharpness impression and alias
can be found. This is signal source and application dependent.
For the luminance channel a filter structure with 10 taps is implemented, and for the
chrominance a filter with 4 taps.
Table 12.
Prescale
ratio
XACL[5:0] example of usage
XPSC
[5:0]
For lower bandwidth requirements
XACL[5:0]
1
0
2
2
(1 2 1)
×
1
4
[1]
3
4
(1 2 2 2 1)
×
1
8
[1]
4
7
(1 1 1 1 1 1 1 1)
×
1
8
[1]
5
8
(1 2 2 2 2 2 2 2 1)
×
1
16
[1]
6
8
(1 2 2 2 2 2 2 2 1)
×
1
16
[1]
7
8
(1 2 2 2 2 2 2 2 1)
×
1
16
[1]
8
15
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1)
×
1
16
[1]
9
15
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1)
×
1
16
[1]
10
16
(1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1)
×
1
32
[1]
13
16
15
31
16
32
19
32
31
32
32
63
35
63
Recommended values
FIR prefilter
PFY[1:0]/
PFUV[1:0]
For higher bandwidth requirements
XACL[5:0]
XC2_1
0
0
1
0
(1 1)
×
1
2
[1]
3
0
(1 1 1 1)
×
1
4
[1]
4
1
(1 2 2 2 1)
×
1
8
[1]
7
0
(1 1 1 1 1 1 1 1)
×
1
8
[1]
7
0
(1 1 1 1 1 1 1 1)
×
1
8
[1]
7
0
(1 1 1 1 1 1 1 1)
×
1
8
[1]
8
1
(1 2 2 2 2 2 2 2 1)
×
1
16
[1]
8
1
(1 2 2 2 2 2 2 2 1)
×
1
16
[1]
8
1
(1 2 2 2 2 2 2 2 1)
×
1
16
[1]
16
1
16
1
16
1
32
1
32
1
32
1
63
1
XC2_1
0
1
XDCG[2:0]
0
2
XDCG[2:0]
0
1
1
0 to 2
0 to 2
1
2
1
3
1
3
2
2
1
4
0
3
3
2
1
5
1
4
3
2
1
6
1
4
3
3
1
7
1
4
3
3
1
8
0
4
4
3
1
9
0
4
4
3
1
10
1
5
4
3
1
13
1
15
1
16
1
19
1
31
1
32
1
35
1
0
1
1
1
1
1
5
5
6
6
6
7
7
5
5
5
6
6
6
7
3
3
3
3
3
3
3
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