參數(shù)資料
型號(hào): SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 126/175頁
文件大?。?/td> 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
126 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
10.6.9
Subaddress 60h
10.6.10
Subaddresses 61h and 62h
10.7 Programming register interfaces and scaler part
10.7.1
Subaddress 80h
[1]
X = don’t care.
Table 90.
Bit
D6
Slicer status byte 0; 60h[6:2]; read only register
Description
framing code valid
Symbol
FC8V
Value
0
Function
no framing code (0 error) in the last frame
detected
framing code with 0 error detected
no framing code (1 error) in the last frame
detected
framing code with 1 error detected
no VPS in the last frame
VPS detected
no PALplus in the last frame
PALplus detected
no closed caption in the last frame
closed caption detected
1
0
D5
framing code valid
FC7V
1
0
1
0
1
0
1
D4
VPS valid
VPSV
D3
PALplus valid
PPV
D2
closed caption valid
CCV
Table 91.
Subaddress
61h
Slicer status byte 1; 61h[5:0] and slicer status byte 2; 62h[7:0]; read only registers
Bit
Symbol
Description
D5
F21_N
field ID as seen by the VBI slicer; for field 1: D5 = 0
D[4:0]
LN[8:4]
line number
D[7:4]
LN[3:0]
line number
D[3:0]
DT[3:0]
data type; according to
Table 15
62h
Table 92.
SWRST moved to subaddress 88h[5].
Task enable control
Global control 1; global set 80h[6:4]
[1]
Control bits D6 to D4
SMOD
X
X
X
X
0
1
TEB
X
X
0
1
X
X
TEA
0
1
X
X
X
X
Task of register set A is disabled
Task of register set A is enabled
Task of register set B is disabled
Task of register set B is enabled
The scaler window defines the F and V timing of the scaler output
VBI data slicer defines the F and V timing of the scaler output
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