參數(shù)資料
型號: SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 58/175頁
文件大?。?/td> 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
58 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
In
Table 13
and
Table 14
PHO is a usable common phase offset.
It should be noted that the equations of
Figure 40
produce an interpolated output, also for
the unscaled case, as the geometrical reference position for all conversions is the position
of the first line of the lower field; see
Table 13
.
If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference
for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the
1
2
line
phase shift (PHO + 16) that can be skipped. This case is listed in
Table 14
.
The SAF7118 supports 4 phase offset registers per task and component (luminance and
chrominance). The value of 20h represents a phase shift of one line.
The registers are assigned to the following events; e.g. subaddresses B8h to BBh:
B8h: 00 = input field ID 0, task status bit D0 (toggle status; see
Section 8.4.1.3
)
B9h: 01 = input field ID 0, task status bit D1
BAh: 10 = input field ID 1, task status bit D0
BBh: 11 = input field ID 1, task status bit D1
Depending on the input signal (interlaced or non-interlaced) and the task processing
50 Hz or field reduced processing with one or two tasks (see examples in
Section 8.4.1.3
), other combinations may also be possible, but the basic equations are the
same.
Offset =
= 32 = 1 line shift
A =
input line shift = 16
B =
input line shift +
scale increment =
C =
scale increment =
D = no offset = 0
Fig 40. Derivation of the phase related equations (example: interlace vertical scaling
down to
3
5
, with field conversion)
mhb548
field 1
field 2
upper
lower
field 1
field 2
case UP-UP
case LO-LO
field 1
field 2
case UP-LO
case LO-UP
A
B
C
D
-----------
1
2
--
1
2
--
1
2
--
----------------------------
16
+
1
2
--
----------------------------
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