參數(shù)資料
型號(hào)： SAF7118H
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： Multistandard video decoder with adaptive comb filter and component video input
封裝： SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù)： 69/175頁
文件大?。?/td> 898K
代理商： SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
69 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
9.
Input/output interfaces and ports
The SAF7118 has 5 different I/O interfaces:
Analog video input interface, for analog CVBS and/or Yand C input signals and/or
component video signals
Audio clock port
Digital real-time signal port (RT port)
Digital video expansion port (X port), for unscaled digital video input and output
Digital image port (I port) for scaled video data output and programming
Digital host port (H port) for extension of the image port or expansion port from 8-bit
to 16-bit
9.1 Analog terminals
The SAF7118 has 16 analog inputs AI41 to AI44, AI31 to AI34, AI21 to AI24 and
AI11 to AI14 for composite video CVBS or S-video Y/C signal pairs or component video
input signals RGB plus separate sync (or Y-P
B
-P
R
plus separate sync).
Component signals with e.g. sync-on-Y or sync-on-green are also supported; they are fed
to two ADC channels, one for the video contents, the other for sync conversion.
Additionally, there are four differential reference inputs, which must be connected to
ground via a capacitor equivalent to the decoupling capacitors at the 16 inputs. There are
no peripheral components required other than these decoupling capacitors and
18
/56
termination resistors, one set per connected input signal; see application
example in
Figure 92
. Four anti-alias filters are integrated.
Clamp and gain control for the four ADCs are also integrated. An analog video output
(pin AOUT) is provided for testing purposes.
[1]
Pin numbers for QFP160 in parenthesis.
Table 25.
Symbol
AI11 to AI14
Analog pin description
Pin
[1]
J2, K1, K2 and L3
(27, 29, 31 and 34)
AI21 to AI24
G4, G3, H2 and J3
(19, 21, 23 and 26)
AI31 to AI34
E3, F2, F3 and G1
(11, 13, 15 and 18)
AI41 to AI44
B1, D2, D1 and E1
(2, 5, 7 and 10)
AOUT
M1 (36)
I/O
I
Description
analog video signal inputs, e.g.
16 CVBS signals or eight Y/C pairs,
or four RGB plus separate sync (or
Y-P
B
-P
R
plus separate sync) signal
groups can be connected
simultaneously to this device; many
combinations are possible; see
Figure 50
to
Figure 90
Bit
MODE5 to
MODE0
O
analog video output, for test
purposes
analog reference pins for differential
ADC operation; connect to ground
via 47 nF
AOSL2 to
AOSL0
-
AI1D, AI2D,
AI3D and AI4D
K3, H1, F1 and D3
(30, 22, 14 and 6)
I
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