參數(shù)資料
型號： SAF7118H
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： Multistandard video decoder with adaptive comb filter and component video input
封裝： SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù)： 127/175頁
文件大?。?/td> 898K
代理商： SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
127 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
X = don’t care.
[2]
Although the ICLK I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.
10.7.2
Subaddresses 83h to 87h
[1]
X = don’t care.
Table 93.
I port and scaler back-end clock selection
Global control 1; global set 80h[3:0]
[1]
Control bits D3 to D0
ICKS3
X
X
X
X
X
X
0
1
ICKS2
X
X
X
[2]
X
0
1
X
X
ICKS1
0
0
1
1
X
X
X
X
ICKS0
0
1
0
1
X
X
X
X
ICLK output and back-end clock is line-locked clock LLC from decoder
ICLK output and back-end clock is XCLK from X port
ICLK output is LLC and back-end clock is LLC2 clock
Back-end clock is the ICLK input
IDQ pin carries the data qualifier
IDQ pin carries a gated back-end clock (DQ AND CLK)
IDQ generation only for valid data
IDQ qualifies valid data inside the scaling region and all data outside the
scaling region
Table 94.
Output clock phase control
X port I/O enable and output clock phase control; global set 83h[5:4]
Control bits D5 and D4
XPCK1
0
0
1
1
XPCK0
0
1
0
1
XCLK default output phase, recommended value
XCLK output inverted
XCLK phase shifted by approximately 3 ns
XCLK output inverted and shifted by approximately 3 ns
Table 95.
X port I/O enable
X port I/O enable and output clock phase control; global set 83h[2:0]
[1]
Control bits D2 to D0
XRQT
X
X
X
X
0
1
XPE1
0
0
1
1
X
X
XPE0
0
1
0
1
X
X
X port output is disabled by software
X port output is enabled by software
X port output is enabled by pin XTRI at logic 0
X port output is enabled by pin XTRI at logic 1
XRDY output signal is A/B task flag from event handler (A = 1)
XRDY output signal is ready signal from scaler path (XRDY = 1 means
the SAF7118 is ready to receive data)
Table 96.
I port signal definitions
I port signal definitions; global set 84h[7:6] and 86h[5]
Control bits
86h[5]
IDG02
0
0
0
84h[7:6]
IDG01
0
0
1
IDG00
0
1
0
IGP0 is output field ID, as defined by OFIDC[90h[6]]
IGP0 is A/B task flag, as defined by CONLH[90h[7]]
IGP0 is sliced data flag, framing the sliced VBI data at the I port
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SAF7129AH/V1,518 功能描述:視頻 IC 6 DAC VIDEO ENCODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAF7129AH/V1,557 功能描述:視頻 IC 6 DAC VIDEO ENCODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
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