參數(shù)資料
型號： SAF7118H
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： Multistandard video decoder with adaptive comb filter and component video input
封裝： SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù)： 123/175頁
文件大小： 898K
代理商： SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
123 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
10.5 Programming register audio clock generation
See equations in
Section 8.7
and examples in
Table 22
and
Table 23
.
10.5.1
Subaddresses 30h to 32h
10.5.2
Subaddresses 34h to 36h
10.5.3
Subaddress 38h
10.5.4
Subaddress 39h
10.5.5
Subaddress 3Ah
Table 77.
Subaddress
30h
31h
32h
Audio master clock (AMCLK) cycles per field
Control bits D7 to D0
ACPF7
ACPF6
ACPF15
ACPF14
-
-
ACPF5
ACPF13
-
ACPF4
ACPF12
-
ACPF3
ACPF11
-
ACPF2
ACPF10
-
ACPF1
ACPF9
ACPF17
ACPF0
ACPF8
ACPF16
Table 78.
Subaddress
34h
35h
36h
Audio master clock (AMCLK) nominal increment
Control bits D7 to D0
ACNI7
ACNI6
ACNI15
ACNI14
-
-
ACNI5
ACNI13
ACNI21
ACNI4
ACNI12
ACNI20
ACNI3
ACNI11
ACNI19
ACNI2
ACNI10
ACNI18
ACNI1
ACNI9
ACNI17
ACNI0
ACNI8
ACNI16
Table 79.
Subaddress
38h
Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK)
Control bits D7 to D0
-
-
SDIV5
SDIV4
SDIV3
SDIV2
SDIV1
SDIV0
Table 80.
Subaddress
39h
Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK)
Control bits D7 to D0
-
-
LRDIV5
LRDIV4
LRDIV3
LRDIV2
LRDIV1
LRDIV0
Table 81.
Bit
D3
Audio clock control; 3Ah[3:0]
Description
audio PLL modes
Symbol
APLL
Value
0
1
0
Function
PLL active, AMCLK is field-locked
PLL open, AMCLK is free-running
vertical reference pulse is taken from internal
decoder
vertical reference is taken from XRV input
(expansion port)
ALRCLK edges triggered by falling edges of
ASCLK
ALRCLK edges triggered by rising edges of
ASCLK
ASCLK edges triggered by falling edges of
AMCLK
ASCLK edges triggered by rising edges of AMCLK
D2
audio master clock vertical
reference
AMVR
1
D1
ALRCLK phase
LRPH
0
1
D0
ASCLK phase
SCPH
0
1
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