參數(shù)資料
型號: SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 138/175頁
文件大?。?/td> 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
138 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
X = don’t care.
10.7.10
Subaddresses A4h to A6h
Table 126. Prescaler DC gain and FIR prefilter control; register set A [A2h[3:0]] and B [D2h[3:0]]
[1]
Prescaler DC gain
Control bits D3 to D0
XC2_1
X
X
X
X
X
X
X
X
0
XDCG2
0
0
0
0
1
1
1
1
X
XDCG1
0
0
1
1
0
0
1
1
X
XDCG0
0
1
0
1
0
1
0
1
X
Prescaler output is renormalized by gain factor = 1
Prescaler output is renormalized by gain factor =
1
2
Prescaler output is renormalized by gain factor =
1
4
Prescaler output is renormalized by gain factor =
1
8
Prescaler output is renormalized by gain factor =
1
16
Prescaler output is renormalized by gain factor =
1
32
Prescaler output is renormalized by gain factor =
1
64
Prescaler output is renormalized by gain factor =
1
128
Weighting of all accumulated samples is factor ‘1’;
e.g. XACL = 4
sequence 1 + 1 + 1 + 1 + 1
Weighting of samples inside sequence is factor ‘2’;
e.g. XACL = 4
sequence 1 + 2 + 2 + 2 + 1
1
X
X
X
Table 127. Luminance brightness control; register set A [A4h[7:0]] and B [D4h[7:0]]
Luminance brightness
control
BRIG7
BRIG6
Value = 0
0
0
Nominal value = 128
1
0
Value = 255
1
1
Control bits D7 to D0
BRIG5
0
0
1
BRIG4
0
0
1
BRIG3
0
0
1
BRIG2
0
0
1
BRIG1
0
0
1
BRIG0
0
0
1
Table 128. Luminance contrast control; register set A [A5h[7:0]] and B [D5h[7:0]]
Luminance contrast control Control bits D7 to D0
CONT7
Gain = 0
0
Gain =
1
64
0
Nominal gain = 64
0
Gain =
127
64
0
CONT6
0
0
1
1
CONT5
0
0
0
1
CONT4
0
0
0
1
CONT3
0
0
0
1
CONT2
0
0
0
1
CONT1
0
0
0
1
CONT0
0
1
0
1
Table 129. Chrominance saturation control; register set A [A6h[7:0]] and B [D6h[7:0]]
Chrominance saturation
control
SATN7
SATN6
Gain = 0
0
0
Gain =
1
64
0
0
Nominal gain = 64
0
1
Gain =
127
64
0
1
Control bits D7 to D0
SATN5
0
0
0
1
SATN4
0
0
0
1
SATN3
0
0
0
1
SATN2
0
0
0
1
SATN1
0
0
0
1
SATN0
0
1
0
1
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