參數(shù)資料
型號： SAF7118H
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： Multistandard video decoder with adaptive comb filter and component video input
封裝： SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù)： 137/175頁
文件大?。?/td> 898K
代理商： SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
137 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
If the desired output length is greater than the number of scaled output lines, the processing is cut.
10.7.9
Subaddresses A0h to A2h
[1]
X = don’t care.
Table 122. Vertical output window length; register set A [9Eh[7:0]; 9Fh[3:0]] and B [CEh[7:0]; CFh[3:0]]
Vertical output acquisition window
definition number of desired output
lines in Y (vertical) direction
B [CFh[3:0]]
YD11 YD10 YD9
No output
0
0
1 pixel
0
0
Maximum possible number of output
lines = 4095
[1]
Control bits
A [9Fh[3:0]] and
A [9Eh[7:0]] and B [CEh[7:0]]
YD8
0
0
1
YD7
0
0
1
YD6
0
0
1
YD5
0
0
1
YD4
0
0
1
YD3
0
0
1
YD2
0
0
1
YD1
0
0
1
YD0
0
1
1
0
0
1
1
1
Table 123. Horizontal prescaling; register set A [A0h[5:0]] and B [D0h[5:0]]
Horizontal integer prescaling ratio (XPSC)
Control bits D5 to D0
XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0
0
0
0
0
0
0
0
0
0
...
...
...
1
1
1
Not allowed
Downscale = 1
Downscale =
1
2
...
Downscale =
1
63
0
0
0
...
1
0
0
1
...
1
0
1
0
...
1
Table 124. Accumulation length; register set A [A1h[5:0]] and B [D1h[5:0]]
Horizontal prescaler accumulation sequence length (XACL)
Control bits D5 to D0
XACL5
XACL4
0
0
0
0
...
...
1
1
XACL3
0
0
...
1
XACL2
0
0
...
1
XACL1
0
0
...
1
XACL0
0
1
...
1
Accumulation length = 1
Accumulation length = 2
...
Accumulation length = 64
Table 125. Prescaler DC gain and FIR prefilter control; register set A [A2h[7:4]] and B [D2h[7:4]]
[1]
FIR prefilter control
Control bits D7 to D4
PFUV1
X
X
X
X
0
0
1
1
PFUV0
X
X
X
X
0
1
0
1
PFY1
0
0
1
1
X
X
X
X
PFY0
0
1
0
1
X
X
X
X
Luminance FIR filter bypassed
H_y(z) =
1
4
(1 2 1)
H_y(z) =
1
8
(
1 1 1.75 4.5 1.75 1
1)
H_y(z) =
1
8
(1 2 2 2 1)
Chrominance FIR filter bypassed
H_uv(z) =
1
4
(1 2 1)
H_uv(z) =
1
32
(3 8 10 8 3)
H_uv(z) =
1
8
(1 2 2 2 1)
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