參數(shù)資料
型號: SAF7118H
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Multistandard video decoder with adaptive comb filter and component video input
封裝: SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;SAF7118EH/V1<SOT807-1 (HBGA156)|<<http://www.nxp.com/packages/SOT807-1.html<1<,;
文件頁數(shù): 130/175頁
文件大?。?/td> 898K
代理商: SAF7118H
SAF7118_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
130 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
[1]
X = don’t care.
[1]
X = don’t care.
[2]
IPCK3 and IPCK2 only affect the gated clock (subaddress 80h, bit ICKS2 = 1).
Table 102. I port FIFO flag control and arbitration; global set 86h[3:0]
[1]
I port FIFO flag control and arbitration
Control bits D3 to D0
FFL1
FFL0
FEL1
FEL0
FAE FIFO flag almost empty level
< 16 double words
< 8 double words
< 4 double words
0 double words
FAF FIFO flag almost full level
16 double words
24 double words
28 double words
32 double words
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
Table 103. I port I/O enable, output clock and gated clock phase control; global set 87h[7:4]
[1]
Output clock and gated clock phase control
Control bits D7 to D4
IPCK3
[2]
X
X
IPCK2
[2]
X
X
IPCK1
0
0
IPCK0
0
1
ICLK default output phase
ICLK phase shifted by
1
2
clock cycle
recommended for ICKS1 = 1 and
ICKS0 = 0 (subaddress 80h)
ICLK phase shifted by approximately 3 ns
ICLK phase shifted by
1
2
clock cycle + approximately
3 ns
alternatively to setting ‘01’
IDQ = gated clock default output phase
IDQ = gated clock phase shifted by
1
2
clock cycle
recommended for
gated clock output
IDQ = gated clock phase shifted by approximately 3 ns
IDQ = gated clock phase shifted by
1
2
clock cycle + approximately
3 ns
alternatively to setting ‘01’
X
X
X
X
1
1
0
1
0
0
0
1
X
X
X
X
1
1
0
1
X
X
X
X
Table 104. I port I/O enable, output clock and gated clock phase control; global set 87h[1:0]
I port I/O enable
Control bits D1 and D0
IPE1
0
0
1
1
IPE0
0
1
0
1
I port output is disabled by software
I port output is enabled by software
I port output is enabled by pin ITRI at logic 0
I port output is enabled by pin ITRI at logic 1
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