參數(shù)資料
型號: S71AL016M40
廠商: Spansion Inc.
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory and RAM
中文描述: 堆疊式多芯片產品(MCP)的閃存和RAM
文件頁數(shù): 64/68頁
文件大?。?/td> 728K
代理商: S71AL016M40
64
S71AL016M
S71AL016M_M0_A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
Notes:
1.
2.
High-Z and Low-Z parameters are characterized and are not 100% tested.
The internal write time of the memory is defined by the overlap of WE#, CE#1 = V
IL
, CE2 = V
IH
, B
HE
and/or B
LE
= V
IL
. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set-
up and hold timing should be referenced to the edge of the signal that terminates write.
3.
Data I/O is high impedance if OE#
V
IH
.
4.
If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
5.
During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
Figure 26. Write Cycle 1 (WE# Controlled)
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