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| 型號： | S71AL016M40 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM |
| 文件頁數(shù)： | 41/68頁 |
| 文件大?。?/td> | 728K |
| 代理商： | S71AL016M40 |
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February 23, 2005 S71AL016M_M0_A0
S71AL016M
41
A d v a n c e I n f o r m a t i o n
selected for erasure. Thus, both status bits are required for sector and mode in-
formation. Refer to
Table 11 on page 43
to compare outputs for DQ2 and DQ6.
Figure 8, on page 42
shows the toggle bit algorithm in flowchart form, and the
section
Reading Toggle Bits DQ6/DQ2 on page 41
explains the algorithm. See
also the
DQ6: Toggle Bit I on page 40
subsection.
Figure 18, on page 52
shows
the toggle bit timing diagram.
Figure 19, on page 53
shows the differences be-
tween DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 8, on page 42
for the following discussion. Whenever the system
initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in
a row to determine whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device completed the program or erase opera-
tion. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the tog-
gle bit is still toggling, the system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer toggling, the device
successfully completed the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 did not go high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of
Figure
8, on page 42
).
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