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參數(shù)資料
| 型號： | S71AL016M40 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM |
| 文件頁數(shù)： | 32/68頁 |
| 文件大?。?/td> | 728K |
| 代理商： | S71AL016M40 |
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32
S71AL016M
S71AL016M_M0 A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
Notes:
See Tables 10 and for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does
not
re-
quire the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to provide any con-
trols or timings during these operations.
Table 10 on page 37
and
Table 11 on
page 43
show the address and data requirements for the chip erase command
sequence.
Note that the SecSi Sector, autoselect, and CFI functions are un-
available when an erase operation is in progress.
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a
hardware reset
during the chip erase operation
immediately terminates the operation. The Chip Erase command sequence
should be reinitiated once the device returns to reading array data, to ensure
data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See
Autoselect Command Sequence on page 30
for informa-
tion on these status bits. When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no longer latched.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
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