參數(shù)資料
型號: S71AL016M40
廠商: Spansion Inc.
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory and RAM
中文描述: 堆疊式多芯片產品(MCP)的閃存和RAM
文件頁數(shù): 18/68頁
文件大?。?/td> 728K
代理商: S71AL016M40
18
S71AL016M
S71AL016M_M0 A0 February 23, 2005
A d v a n c e I n f o r m a t i o n
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
The device features an
Unlock Bypass
mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The
Word Program Command
Sequence on page 31
contains details on programming data to the device using
both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 2 and 3 indicate the address space that each sector occupies. A “sector
address” consists of the address bits required to uniquely select a sector. The
Command Definitions on page 29
contains details on erasing a sector or the en-
tire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters
the autoselect mode. The system can then read autoselect codes from the inter-
nal register (which is separate from the memory array) on DQ7–DQ0. Standard
read cycle timings apply in this mode. Refer to the
Autoselect Mode on page 22
and
Autoselect Command Sequence on page 30
sections for more information.
I
CC2
in the DC Characteristics table represents the active current specification
for the write mode. The
AC Characteristics on page 47
section contains timing
specification tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the
operation by reading the status bits on DQ7–DQ0. Standard read cycle timings
and I
CC
read specifications apply. Refer to
Write Operation Status on page 38
for more information, and to
AC Characteristics on page 47
for timing
diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V
CC
±
0.3 V. (Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within V
CC
±
0.3 V, the device
is in the standby mode, but the standby current is greater. The device requires
standard access time (t
CE
) for read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the DC Characteristics table, I
CC3
and I
CC4
represents the standby current
specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE#
control signals. Standard address access timings provide new data when ad-
dresses are changed. While in sleep mode, output data is latched and always
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