參數(shù)資料
型號： S71AL016M40
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory and RAM
中文描述： 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM
文件頁數(shù)： 29/68頁
文件大?。?/td> 728K
代理商： S71AL016M40
February 23, 2005 S71AL016M_M0_A0
S71AL016M
29
A d v a n c e I n f o r m a t i o n
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or eras-
ing provides data protection against inadvertent writes (refer to
Table 10 on
page 37
and
Table 11 on page 43
for command definitions). In addition, the fol-
lowing hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level sig-
nals during V
CC
power-up and power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This
protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the device resets. Subse-
quent writes are ignored until V
CC
is greater than V
LKO
. The system must
provide the proper signals to the control pins to prevent unintentional writes
when V
CC
is greater than V
LKO
.
Write Pulse
Glitch
Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a
write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
or WE# =
V
IH
. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations.
Table 10 on page 37
and
Table 11 on
page 43
define the valid register command sequences.
Note that writing incor-
rect address and data values or writing them in the improper sequence may
place the device in an unknown state. A reset command is then required to set
the device for the next operation.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in
AC Characteristics on page 47
.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
Erase Suspend mode. The system can read array data using the standard read
4Bh
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Table 9. Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Addresses
Data
Description
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