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| 型號： | S71AL016M40 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM |
| 文件頁數(shù)： | 17/68頁 |
| 文件大?。?/td> | 728K |
| 代理商： | S71AL016M40 |
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February 23, 2005 S71AL016M_M0_A0
S71AL016M
17
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command regis-
ter itself does not occupy any addressable memory location. The register is
composed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device.
Table 1
lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1.
Addresses are A19:A0 in word mode.
2.
The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
IL
. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at V
IH
.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access until the command
register contents are altered.
See
Reading Array Data on page 29
for more information. Refer to
Table 14 on
page 47
for timing specifications and to
Figure 13, on page 47
for the timing di-
agram. I
CC1
in the DC Characteristics table represents the active current
specification for reading array data.
Table 1. S29AL016M Device Bus Operations
Operation
CE#
L
L
V
CC
±
0.3 V
L
X
OE#
L
H
WE#
H
L
RESET#
H
H
V
CC
±
0.3 V
H
L
Addresses
(Note 1)
A
IN
A
IN
DQ00–
DQ15
D
OUT
D
IN
Read
Write
Standby
X
X
X
High-Z
Output Disable
Reset
H
X
H
X
X
X
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
D
IN
Sector Unprotect (Note 2)
L
H
L
V
ID
D
IN
Temporary Sector
Unprotect
X
X
X
V
ID
A
IN
D
IN
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