參數(shù)資料
型號(hào)： S71AL016M40
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory and RAM
中文描述： 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM
文件頁(yè)數(shù)： 31/68頁(yè)
文件大?。?/td> 728K
代理商： S71AL016M40
February 23, 2005 S71AL016M_M0_A0
S71AL016M
31
A d v a n c e I n f o r m a t i o n
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is
not
required to provide further
controls or timings. The device automatically generates the program pulses and
verifies the programmed cell margin. Tables
10
–
11
show the address and data
requirements for the program command sequence.
Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when a program operation is in
progress.
When the Embedded Program algorithm is complete, the device then returns to
reading array data and addresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See
Write Operation Status on page 38
for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a
hardware reset
immediately terminates the program-
ming operation. The Program command sequence should be reinitiated once the
device resets to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. Pro-
gramming to the same address multiple times without intervening erases is
limited. For such application requirements, please contact your local Spansion
representative.
Any bit in a word or byte
cannot be programmed from
0
back to a
1
.
Attempting to do so may halt the operation and set DQ5 to “1,” or
cause the Data# Polling algorithm to indicate the operation was successful.
However, a succeeding read shows that the data is still
0
. Only erase operations
can convert a
0
to a
1
.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles re-
quired in the standard program command sequence, resulting in faster total
programming time.
Table 10 on page 37
and
Table 11 on page 43
show the re-
quirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock
Bypass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first
cycle must contain the data 90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to reading array data.
Figure 4, on page 32
illustrates the algorithm for the program operation. See
Table 18 on page 57
for parameters, and to
Figure 17, on page 55
for timing
diagrams.
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