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參數(shù)資料
| 型號： | S71AL016M40 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM |
| 文件頁數(shù)： | 19/68頁 |
| 文件大小： | 728K |
| 代理商： | S71AL016M40 |
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February 23, 2005 S71AL016M_M0_A0
S71AL016M
19
A d v a n c e I n f o r m a t i o n
available to the system. I
CC4
in the DC Characteristics table represents the auto-
matic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the system drives the RESET# pin to V
IL
for at least a period
of t
RP
, the device
immediately terminates
any operation in progress, tristates
all data output pins, and ignores all read/write attempts for the duration of the
RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
SS
±0.3 V, the device draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
READY
(during Embedded Algorithms). The system can thus monitor
RY/BY# to determine whether the reset operation is complete. If RESET# is as-
serted when a program or erase operation is not executing (RY/BY# pin is “1”),
the reset operation is completed within a time of t
READY
(not during Embedded
Algorithms). The system can read data t
RH
after the RESET# pin returns to V
IH
.
Refer to the
AC Characteristics on page 47
tables for RESET# parameters and
to
Figure 14, on page 48
for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is disabled. The output
pins are placed in the high impedance state.
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