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| 型號(hào)： | RG82845 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 88/157頁(yè) |
| 文件大?。?/td> | 1407K |
| 代理商： | RG82845 |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
36
Datasheet
250687-002
R
3.
Register Description
3.1.
Conceptual Overview of the Platform Configuration
Structure
The Intel 845MP/845MZ Chipset MCH-M and ICH3-M are physically connected by hub interface A.
From a configuration standpoint, the hub interface A is PCI bus #0. As a result, all devices internal to the
MCH-M and ICH3-M appear to be on PCI bus #0. The system’s primary PCI expansion bus is physically
attached to the ICH3-M and from a configuration perspective, appears to be a hierarchical PCI bus
behind a PCI-to-PCI bridge and therefore has a programmable PCI Bus number. Note that the primary
PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a configuration
standpoint. The AGP appears to system software to be a real PCI bus behind PCI-to-PCI bridges
resident as devices on PCI bus #0.
The MCH-M contains two PCI devices within a single physical component. The configuration registers
for the four devices are mapped as devices residing on PCI bus #0.
Device 0: Host-hub interface Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI bus #0. Physically Device 0 contains the standard PCI registers, DRAM registers,
the Graphics Aperture controller, and other MCH-M specific registers.
Device 1: Host-AGP Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residing on
PCI bus #0. Physically Device 1 contains the standard PCI-to-PCI bridge registers and the standard
AGP/PCI configuration registers (including the AGP I/O and memory address mapping).
The following table shows the Device # assignment for the various internal MCH-M devices.
Table 19. Device Number Assignment
MCH-M Function
Bus #0, Device#
DRAM Controller/8 bit HI_A Controller
Device #0
Host-to-AGP Bridge (virtual P2P)
Device #1
NOTE:
A physical PCI bus #0 does not exist. The hub interface and the internal devices in the Intel 845MP/845MZ
Chipset MCH-M and ICH3-M logically constitute PCI Bus #0 to configuration software.
3.2.
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the CPU. Configuration space is supported by a
mapping mechanism implemented within the MCH-M. The PCI specification defines two mechanisms to
access configuration space, Mechanism #1 and Mechanism #2. The MCH-M supports only Mechanism
#1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RG82845MP | Controller Miscellaneous - Datasheet Reference |
| RG82845MZ | Controller Miscellaneous - Datasheet Reference |
| RG82870P2 | Controller Miscellaneous - Datasheet Reference |
| RH5RE36AA-T1-FA | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RH5RE56AA-T1-FA | 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RG82845 S L5V7 | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 S L5YQ | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 S L63W | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 SL5V7 | 制造商:Intel 功能描述: |
| RG82845E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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