Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
118
Datasheet
250687-002
R
AGP PIPE# or SBA[7:0] protocol transactions to DRAM do not get snooped and are, therefore, not
coherent with the processor caches. AGP FRAME# protocol transactions to DRAM are snooped. AGP
PIPE# and SBA[7:0] accesses to and from the hub interface are not supported. AGP FRAME# access
from an AGP master to the hub interface are also not supported. Only AGP FRAME# memory writes
from the hub interface are supported.
5.3.1.
AGP Target Operations
The MCH-M supports AGP cycles targeting main memory only. The MCH-M supports interleaved AGP
PIPE#] and AGP FRAME# transactions, or AGP SBA[7:0] and AGP FRAME# transactions.
Table 29. AGP Commands Supported by the MCH-M When Acting as an AGP Target
MCH-M Host Bridge
AGP
Command
C/BE[3:0]#
Encoding
Cycle Destination
Response as PCIx Target
Read
0000
Main Memory
Low Priority Read
0000
The Hub interface
Complete with random data; does not go to the hub
interface
Hi-Priority Read
0001
Main Memory
High Priority Read
0000
The Hub interface
Complete with random data; does not go to the hub
interface
Reserved
0010
N/A
No Response
Reserved
0011
N/A
No Response
Write
0100
Main Memory
Low Priority Write
0100
The Hub interface
Cycle goes to DRAM with BE’s inactive; does not go to
the hub interface
Hi-Priority Write
0101
Main Memory
High Priority Write
0101
The Hub interface
Cycle goes to DRAM with BE’s inactive; does not go to
the hub interface
Reserved
0110
N/A
No Response
Reserved
0111
N/A
No Response
Long Read
1000
Main Memory
Low Priority Read
The Hub interface
Complete with random data; does not go to the hub
interface
Hi-Priority Long
Read
1001
Main Memory
High Priority Read
The Hub interface
Complete with random data; does not go to the hub
interface
Flush
1010
MCH-M
Complete with QW of Random Data
Reserved
1011
N/A
No Response
Fence
1100
MCH-M
No Response - Flag inserted in MCH-M request queue
Reserved
1101
N/A
No Response
Reserved
1110
N/A
No Response