參數(shù)資料
型號(hào)： RG82845
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 50/157頁
文件大?。?/td> 1407K
代理商： RG82845
Intel
845MZ Chipset:82845MZ (MCH-M)
250687-001
Datasheet
143
R
9.4.
Testability
In the
MCH-M, testability for Automated Test Equipment (ATE) board level testing has been implemented
as and XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it. Refer to
Figure 11 for an example XOR chain.
Figure 11. XOR–Tree Chain
Input
XOR
Out
xor.vsd
Input
VCC1_8
The algorithm used for in –circuit test is as follows
Drive all input pins to an initial logic level ‘1’. Observe the output corresponding to scan chain being
tested.
Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin, from its
initial logic level to the opposite logic level. Observe the output changes with each pin toggle.
9.4.1.
XOR Test Mode Initialization
XOR test mode can be entered by pulling three shared pins (reset straps) low through the rising transition
of RSTINB. The signals that need to be pulled are as follows:
GGNTB = 0 (Global strap enable)
SBA[1]
= 0 (XOR strap)
ST[2]
= 0 (PLL Bypass mode; it is recommended to enter PLL Bypass in XOR test mode)
相關(guān)PDF資料
PDF描述
RG82845MP Controller Miscellaneous - Datasheet Reference
RG82845MZ Controller Miscellaneous - Datasheet Reference
RG82870P2 Controller Miscellaneous - Datasheet Reference
RH5RE36AA-T1-FA 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
RH5RE56AA-T1-FA 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RG82845 S L5V7 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR
RG82845 S L5YQ 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR
RG82845 S L63W 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR
RG82845 SL5V7 制造商:Intel 功能描述:
RG82845E 制造商:Rochester Electronics LLC 功能描述:- Bulk
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