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參數(shù)資料
| 型號： | RG82845 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 27/157頁 |
| 文件大小： | 1407K |
| 代理商： | RG82845 |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
122
Datasheet
250687-002
R
programmed address range are forwarded to the hub interface. MCH-M does not support I/O
accesses from the hub interface to AGP.
Exclusive Access. MCH-M does not issue a locked cycle on the AGP bus on behalf of either the host
or the hub interface. The hub interface and host locked transactions to AGP are initiated as unlocked
transactions by the MCH-M on the AGP bus.
Configuration Read and Write. Host Configuration cycles to AGP are forwarded as Type 1
Configuration Cycles. MCH-M does not support configuration reads or writes from the hub
interface to AGP.
Fast Back-to-Back Transactions. MCH-M as an initiator does not perform fast back-to-back cycles.
MCH-M Retry/Disconnect Conditions
The MCH-M generates retry/disconnect according to the AGP Specification rules when being accessed
as a target by the AGP master using a FRAME# protocol cycle.
Delayed Transactions
When an AGP FRAME#-to-DRAM read cycle is retried by the MCH-M, it is processed internally as a
Delayed Transaction.
The MCH-M supports the Delayed Transaction mechanism on the AGP target interface for the
transactions issued using AGP FRAME# protocol. This mechanism is compatible with the PCI 2.1
Specification. The process of latching all information required to complete the transaction, terminating
with Retry, and completing the request without holding the master in wait-states is called a Delayed
Transaction. The MCH-M latches the Address and Command when establishing a Delayed Transaction.
The MCH-M generates a Delayed Transaction on the AGP only for AGP FRAME# to DRAM read
accesses. The MCH-M does not allow more than one Delayed Transaction access from AGP at any time.
5.4.
Power and Thermal Management
An Intel 845MP/845MZ Chipset platform is compliant with the following specifications:
APM Rev 1.2
ACPI Rev 1.0b
ACPI Rev 2.0
PCI Power Management Rev 1.0
PC'99, Rev 1.0
PC'99A
PC’01, Rev 1.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RG82845MP | Controller Miscellaneous - Datasheet Reference |
| RG82845MZ | Controller Miscellaneous - Datasheet Reference |
| RG82870P2 | Controller Miscellaneous - Datasheet Reference |
| RH5RE36AA-T1-FA | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RH5RE56AA-T1-FA | 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RG82845 S L5V7 | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 S L5YQ | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 S L63W | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 SL5V7 | 制造商:Intel 功能描述: |
| RG82845E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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