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參數(shù)資料
| 型號(hào)： | RG82845 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 14/157頁(yè) |
| 文件大?。?/td> | 1407K |
| 代理商： | RG82845 |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
110
Datasheet
250687-002
R
4.1.9.
Hub Interface A Subtractive Decode
HLA_SUB
From
TOM
To
4GB
All accesses that fall between the value programmed into the TOM register and 4GB are subtractively
decoded and forwarded to hub interface if they do not decode to a space that corresponds to another
device.
4.2.
AGP Memory Address Ranges
The MCH-M can be programmed to direct memory accesses to the AGP bus interface when addresses
are within either of two ranges specified via registers in MCH-M Device #1 configuration space. The
first range is controlled via the Memory Base Register (MBASE1) and Memory Limit Register
(MLIMIT1) registers. The second range is controlled via the Prefetchable Memory Base (PMBASE1)
and Prefetchable Memory Limit (PMLIMIT1) registers.
The MCH-M positively decodes memory accesses to AGP memory address space as defined by the
following equations:
Memory_Base_Address <= Address =< Memory_Limit_Address
Prefetchable_Memory_Base_Address =< Address <= Prefetchable_Memory_Limit_Address
Plug-and-play configuration software programs the effective size of the range, which depends on the size
of memory claimed by the AGP device.
Note: The MCH-M Device #1 memory range registers described above are used to allocate memory address
space for any devices sitting on AGP bus that requires such a window.
4.2.1.
AGP DRAM Graphics Aperture
Memory-mapped, graphics data structures can reside in a Graphics Aperture to main DRAM memory.
This aperture is an address range defined by the APBASE and APSIZE configuration registers of the
MCH-M device #0. The APBASE register follows the standard base address register template as defined
by the PCI 2.1 specification. The size of the range claimed by the APBASE is programmed via “back-
end” register APSIZE (programmed by the chip-set specific BIOS before plug-and-play session is
performed). APSIZE allows the BIOS software to pre-configure the aperture size to be 4 MB, 8 MB, 16
MB, 32 MB, 64 MB, 128 MB or 256 MB. By programming APSIZE to specific size, the corresponding
lower bits of APBASE are forced to “0” (behave as hardwired). The default value of APSIZE forces an
aperture size of 256 MB. The aperture address range is naturally aligned.
Accesses within the aperture range are forwarded to the main DRAM subsystem. The MCH-M will
translate the originally issued addresses via a translation table maintained in main memory. The aperture
range should be programmed as non-cacheable in the processor caches.
Note: Plug-and-play software configuration model does not allow overlap of different address ranges.
Therefore, the AGP Graphics Aperture and AGP Memory Address Range are independent address
ranges that may abut, but cannot overlap one another.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RG82845MP | Controller Miscellaneous - Datasheet Reference |
| RG82845MZ | Controller Miscellaneous - Datasheet Reference |
| RG82870P2 | Controller Miscellaneous - Datasheet Reference |
| RH5RE36AA-T1-FA | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RH5RE56AA-T1-FA | 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RG82845 S L5V7 | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 S L5YQ | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 S L63W | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 SL5V7 | 制造商:Intel 功能描述: |
| RG82845E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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