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參數(shù)資料
| 型號： | RG82845 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 17/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | RG82845 |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
113
R
All memory read and write accesses to Main DRAM (except SMM space).
All memory write accesses from the hub interface A to AGP memory range defined by MBASE1,
MLIMIT1, PMBASE1, and PMLIMIT1.
All memory read/write accesses to the Graphics Aperture defined by APBASE and APSIZE.
Memory writes to VGA range on AGP if enabled.
All memory reads from the hub interface A that are targeted > 4 GB memory range will be terminated
with Master Abort completion, and all memory writes (>4 GB) from the hub interface A will be ignored.
4.5.2.
AGP Interface Decode Rules
Cycles Initiated Using AGP FRAME# Protocol
The MCH-M does not support any AGP FRAME# access targeting the hub interface A. The MCH-M
will claim AGP initiated memory read and write transactions decoded to the main DRAM range or the
Graphics Aperture range. All other memory read and write requests will be master-aborted by the AGP
initiator as a consequence of MCH-M not responding to a transaction.
The MCH-M forwards AGP/PCI accesses addressed to the DOS Compatibility ranges between
0C0000h-0FFFFFh to main memory, regardless of the configuration of the Programmable Attributes
Map registers (PAM registers). The PAM registers govern the destination of host CPU accesses to the
DOS Compatibility ranges but do not similarly affect the destination of AGP/PCI accesses to this range.
MCH-M will forward to main memory any AGP/PCI initiated access to the PAM areas. Note that the
MCH-M may hang if an AGP originated access occurs to a Read Disabled or Write Disabled PAM
segment. Therefore, the following critical restriction is placed on the programming of the PAM regions:
at the time that an AGP accesses to a PAM region occurs, the targeted PAM segment must be
programmed to be both readable and writable. If an AGP master issues an I/O, PCI Configuration or PCI
Special Cycle transaction, the MCH-M will not respond and cycle will result in a master-abort.
Cycles Initiated Using AGP PIPE# or SBA Protocol
All cycles must reference main memory i.e. main DRAM address range (including PAM) or Graphics
Aperture range (also physically mapped within DRAM but using different address range). AGP accesses
to SMM space are not allowed. AGP protocol cycles that target DRAM are not snooped on the host bus,
even if they fall outside of the AGP aperture range.
If a cycle is outside of main memory range then it will terminate as follows:
Reads: remapped to memory address 0h, data returned from address 0h, and IAAF error bit set in
ERRSTS register in device #0
Writes: dropped “on the floor” i.e. terminated internally without affecting any buffers or main
memory
AGP Accesses to MCH-M that Cross Device Boundaries
The MCH-M will disconnect AGP FRAME# transactions on 4KB boundaries.
AGP PIPE# and SBA accesses are limited to 256 bytes and must hit DRAM. Read accesses crossing out
of DRAM will return invalid data, and the IAAF Error bit will be set. Write accesses crossing out of
DRAM will be discarded, and the IAAF Error bit will be set.
相關PDF資料 |
PDF描述 |
|---|---|
| RG82845MP | Controller Miscellaneous - Datasheet Reference |
| RG82845MZ | Controller Miscellaneous - Datasheet Reference |
| RG82870P2 | Controller Miscellaneous - Datasheet Reference |
| RH5RE36AA-T1-FA | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RH5RE56AA-T1-FA | 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| RG82845 S L5V7 | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 S L5YQ | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 S L63W | 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR |
| RG82845 SL5V7 | 制造商:Intel 功能描述: |
| RG82845E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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