參數(shù)資料
型號(hào)： RG82845
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 140/157頁
文件大?。?/td> 1407K
代理商： RG82845
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
83
R
3.7.37.
SMICMD – SMI Command Register – Device #0
Address Offset:
CC-CDh
Default Value:
0000h
Access:
Read/Write, Read Only
Size:
16 bits
This register enables various errors to generate an SMI message via the hub interface A.
Note: An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SMI error message is enabled for an error condition; SERR and
SCI error messages are disabled for that same error condition.
Bit
Description
15:2
Reserved
1
SMI on Multiple-bit DRAM ECC Error (DMERR): When this bit is set, the generation of the hub
interface A SMI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.
For systems not supporting ECC this bit must be disabled.
0
SMI on Single-bit ECC Error (DSERR): When this bit is set, the generation of the hub interface A
SMI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.
3.7.38.
SCICMD – SCI Command Register – Device #0
Address Offset:
CE-CDh
Default Value:
0000h
Access:
Read/Write, Read Only
Size:
16 bits
This register enables various errors to generate a SCI message via the hub interface A.
Note: An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SCI error message is enabled for an error condition, SERR and
SMI error messages are disabled for that same error condition.
Bit
Description
15:2
Reserved
1
SCI on Multiple-Bit DRAM ECC Error (DMERR): When this bit is set, the generation of the hub
interface A SCI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.
For systems not supporting ECC this bit must be disabled.
0
SCI on Single-bit ECC Error (DSERR): When this bit is set, the generation of the hub interface A
SCI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.
相關(guān)PDF資料
PDF描述
RG82845MP Controller Miscellaneous - Datasheet Reference
RG82845MZ Controller Miscellaneous - Datasheet Reference
RG82870P2 Controller Miscellaneous - Datasheet Reference
RH5RE36AA-T1-FA 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
RH5RE56AA-T1-FA 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RG82845 S L5V7 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR
RG82845 S L5YQ 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR
RG82845 S L63W 制造商:Intel 功能描述:MEMORY CONTROLLER HUB (MCH) FOR SDR
RG82845 SL5V7 制造商:Intel 功能描述:
RG82845E 制造商:Rochester Electronics LLC 功能描述:- Bulk
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