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參數(shù)資料
| 型號： | PM7329 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | ATM TRAFFIC MANAGER AND SWITCH |
| 中文描述： | ATM流量管理器和開關(guān) |
| 文件頁數(shù)： | 74/232頁 |
| 文件大?。?/td> | 1585K |
| 代理商： | PM7329 |
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PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
60
If a write transaction is indicated at the address cycle, then S/UNI-APEX-1K800
will respond with a ready indicator concurrent with each long word of valid data,
until the burst is complete. The delay between the address cycle and the first
valid long word of write data is variable, depending on the specific register
address (not less than 1 clock cycle). If a write transaction is issued to the
transmit SAR when the buffer is full, or issued to the memory port when the
current command is not yet complete, the first word of valid write data will be
delayed by the ready indicator until buffer space is available (this can be many
clock cycles). If excessive delay for the first word of valid write data cannot be
tolerated, then polling (or interrupt processing) must be used for accesses to
these regions. Once the ready indicator has been asserted, it will remain
asserted until the completion of the burst.
An additional output is provided to indicate when the current write operation is
complete (write done indicator). Processors which do not allow the ready
indicator to be used to delay the advance of write data, but do allow a write
operation to be delayed before it is issued (such as the IDT MIPS processor)
may use this output. The write done indicator is asserted when S/UNI-APEX-
1K800 can accept another write command. Typically, an external circuit may be
employed which uses this S/UNI-APEX-1K800 output to determine when to allow
the processor to issue another write command. When this output is used prior to
the address cycle, the normal ready indicator need not be used for write
operations, as S/UNI-APEX-1K800 can accept write data always once the write
done indicator is asserted (unless polling of buffer status is disabled). Note that
polling of buffer status must be employed when the processor does not allow the
ready indicator to be used to delay the advance of write data.
If a burst is indicated at the address cycle, then the transaction will not complete
until the processor asserts the burst last indicator. If a burst is not indicated, then
the transaction will be completed after the ready indicator is asserted by S/UNI-
APEX-1K800.
The multiplexed address/data bus will be Hi-Z’d immediately following the last
word of read data to allow a new address cycle to commence. The
microprocessor interface will allow an address cycle to occur with no wait states
between the last word of valid data and the new address; however, care must be
taken to minimize bus contention in the system design if no wait states are
provided by the microprocessor.
The diagrams below illustrate possible connections between the S/UNI-APEX-
1K800 and various microprocessors. For the i960 interface, the two lower order
bits of the address may be tied to ground as all accesses to the S/UNI-APEX-
1K800 are 32bits wide.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7329-BI | 制造商:PMC 制造商全稱:PMC 功能描述:ATM TRAFFIC MANAGER AND SWITCH |
| PM733 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| PM7339 | 制造商:PMC 制造商全稱:PMC 功能描述:SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK |
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