![](http://datasheet.mmic.net.cn/330000/PM7329-BI_datasheet_16444382/PM7329-BI_48.png)
PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
Pin Name
Type
Pin
No.
Function
WTSX
Output
AE21
WAN Transmit Start of Transfer.
WTSX is asserted
by the S/UNI-APEX-1K800 during the first cycle of a
data block transfer. WTSX assertion will coincide
with the port address prepend, if the cell being
transferred has a prepended port address. Required
only during Any-PHY mode.
WTSX is updated on the rising edge of WTCLK.
WTSOP
Output
(Master)
Tri-state
(Slave)
AC19
WAN Transmit Start of Packet.
WTSOP marks the
start of cell on the WTDAT[15:0] data bus. WTSOP
is driven high when the first word of the cell
(excluding address prepend) is present on the
WTDAT[15:0] stream. WTSOP is asserted for each
cell.
In transmit master mode, the signal is always
driven.
In receive slave mode, this signal is driven 1
WTCLK after WTENB is asserted.
WTSOP is updated/Hi-Z’d on the rising edge of
WTCLK.
WTDAT[0]
..
WTDAT[15]
Output
(Master)
Tri-state
(Slave)
AE22
AF23
AC21
AD22
AE23
AF24
AC24
AD26
AC25
AB24
AA23
AC26
AB25
AA24
Y23
AA25
WAN Transmit Data.
WTDAT[15:0] carries the data
block transfers to the physical layer devices.
In 8 bit mode, only WTDAT[7:0] are valid.
In 8/16bit transmit master mode, the entire bus is
always driven.
In receive slave mode, this bus is driven 1 WTCLK
after WTENB is asserted Pull up/downs are
required for the entire bus, regardless of whether
the bus is in 8 or 16 bit mode.
WTDAT[15:0] is updated/Hi-Z’d on the rising edge
of WTCLK.