![](http://datasheet.mmic.net.cn/330000/PM7329-BI_datasheet_16444382/PM7329-BI_122.png)
PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
108
LoopRxICIPreEn:
When set to one, the default, an ICI prepend (Word 1 in Figure 4, Byte 1&2 in
Figure 5) is expected on this interface. When reset to zero an ICI prepend is
not expected on this interface. When in 8 bit mode, this bit must be set to 1.
LoopRxHecDis
When reset to zero, the HEC/UDF field (Word 4 in Figure 4, Byte 7 in Figure
5) is expected on this interface. When set to a one an HEC/UDF field is not
expected on this interface.
LoopRx8bitEn
When reset to zero, this bit sets the interface bus width to 16 bits. When set
to one, this bit sets the interface bus width to 8 bit.
LoopRxParPolarity
When reset to zero, the loop receive parity is odd. When set to one, the loop
receive parity is even.
LoopRxPollAddr[4:0]
In UTOPIA L2 slave mode: The five bit UTOPIA Address to which the slave
will respond.
In Any-PHY and UTOPIA L2 master mode: These bits represents the polling
address range.
LoopRxPollAddr[4:0]
Polling range
0-2
Not valid
3
Address 3->0
…
…
31
Address 31->0
In UTOPIA L1 master mode: These bits are reserved.
LoopRxICISel[1:0]
Indicates which part of the incoming cell, the internal ICI is selected from:
LoopICISel[1:0]
Source
00
User Prepend (Note: LoopRxICIPreEn must be set).
01
VPI/VCI fields:
If the VPI < “FFF” then