![](http://datasheet.mmic.net.cn/330000/PM7329-BI_datasheet_16444382/PM7329-BI_211.png)
PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
197
Figure 42
- Read followed by Write Timing
1
2
3
4
5
6
7
8
9
rd
desel
wr
desel
a1
a1
a2
a2
r1
w2
r1
w2
1cyc
2cyc
sysclk
cmcmd
cmceb
cmrwb
cma[18:0]
mab[18:17]
cmd[33:0]
cmp[1:0]
17.5 Any-PHY/UTOPIA Interfaces
While the following diagrams present representative waveforms, they are not an
attempt to unambiguously describe the interfaces. The Pin Description section is
intended to present the detailed pin behavior and constraints on use.
The following parameters apply to all Any-PHY/UTOPIA interface figures:
n = 2 for WAN, 5 for Loop
m = 7 for 8 bit mode, 15 for 16 bit mode
k = function of 8/16 bit mode, and number of prepends selected.
17.5.1 Receive Master/Transmit Slave Interfaces
Figure 43 gives an example of the functional timing of the receive interface when
configured as a UTOPIA Level 2 compliant transmit slave. The interface
responds to the polling of address “APEX” (which matches the address defined
by the register {Loop/WAN}RxSlaveAddr[n:0]) by asserting RPA when it is
capable of accepting a complete cell. As a result, the master selects the S/UNI-
APEX-1K800 by presenting “APEX” again during the last cycle RENB is high.
Had not the device been selected, RSOP, RDAT[n:0] and RPRTY would have
remained high-impedance.