![](http://datasheet.mmic.net.cn/330000/PM7329-BI_datasheet_16444382/PM7329-BI_53.png)
PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
39
Pin Name
Type
Pin
No.
Function
CBCASB
Output
AC14
Cell Buffer SDRAM Column Address Strobe Bar.
CBCSB, CBRASB, CBCASB, and CBWEB define
the command being sent to the SDRAM.
CBCASB is updated on the rising edge of SYSCLK.
CBWEB
Output
AD14
Cell Buffer SDRAM Write Enable Bar.
CBCSB,
CBRASB, CBCASB, and CBWEB define the
command being sent to the SDRAM.
CBWEB is updated on the rising edge of SYSCLK.
CBA[0]
..
CBA[11]
Output
AC15
AE16
AD16
AE17
AC16
AF18
AD17
AE18
AF19
AC17
AD18
AE19
Cell Buffer SDRAM Address.
The Cell Buffer
SDRAM address outputs identify the row address
(CBA[11:0]) and column address (CBA[7:0]) for the
locations accessed.
CBA[11:0] is updated on the rising edge of
SYSCLK.
CBBS[0]
..
CBBS[1]
Output
AD15
AF16
Cell Buffer SDRAM Bank Select.
The bank select
signal determines which bank of a dual/quad bank
Cell Buffer SDRAM chip is active. CBBS[1:0] is
generated along with the row address when
CBRASB is asserted low.
CBBS is updated on the rising edge of SYSCLK.
CBDQM[0]
..
CBDQM[1]
Output
AE13
AE14
Cell Buffer SDRAM Input/Output Data Mask.
The
data mask changes state from high to low when the
SDRAM is enabled. These pins are held low during
normal operation
CBDQM is updated on the rising edge of SYSCLK.