參數(shù)資料
型號: PM7342
廠商: PMC-Sierra, Inc.
英文描述: 32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY
中文描述: 32連接的ATM反向多路復(fù)用(IMA)系統(tǒng)/單向物理層
文件頁數(shù): 1/2頁
文件大?。?/td> 65K
代理商: PM7342
PM7342
Preliminary
32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY
S/UNI-IMA-32
PMC-2001523 (p5)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Copyright PMC
-
Sierra, Inc. 2002
FEATURES
IMA
Supports up to 32 T1, E1, G.SHDSL or
unchannelized links and up to 32 IMA
groups with 1 to 32 links/group.
Link and Group State Machines
implemented on-chip requiring no real
time software in the data path.
Fully compliant with the ATM Forum
Inverse Multiplexer for ATM (IMA)
1.1 specification and backward
compatible to IMA 1.0.
Supports both independent transmit
clock (ITC) and common transmit clock
(CTC) modes.
Supports all IMA Group Symmetry
modes: Symmetric/Asymmetric
configuration and operation.
Differential delay tolerance of 279 ms
(for T1 links) and 226 ms (for E1 links).
Performs IMA differential delay
calculation and synchronization.
Provides programmable limit on
allowable differential delay and
minimum number of links per group.
Performs ICP and stuff-cell insertion
and removal.
Supports IMA frame length (M) equal
to 32, 64, 128, or 256.
Provides IMA layer statistic counts and
alarms for support of IMA Performance
and Failure Alarm Monitoring and MIB
support.
Provides per link counters for statistics
and performance monitoring.
UNI
Each link is software configurable as
either a UNI or part of an IMA group.
Performs receive cell Header Error
Check (HEC) checking and transmit
cell HEC generation.
Optionally supports receive cell
payload unscrambling and transmit cell
payload scrambling.
Provides TC layer statistics counts and
alarms for MIB support.
ATM OVER FRACTIONAL T1/E1
Supports ATM over Fractional T1/E1
compliant with the ATM Forum
AF-PHY-0130.00 specification.
LINE INTERFACE
32 T1, E1, G.SHDSL or unchannelized
links via 2-pin line interfaces.
Supports a 19.44 MHz Scalable Band-
width Interconnect (SBI) bus interface for
seamless interconnect to the PM8315
TEMUX and PM8316 TEMUX-84.
SBI supports two Synchronous
Payload Envelopes (SPE). Each SPE
can carry up to 16 T1s or 16 E1s.
UTOPIA / ANY-PHY INTERFACE
Supports 8- and 16-bit UTOPIA L2 and
Any-PHY cell interfaces at clock rates
up to 52 MHz.
Any-PHY transmit slave appears as a
32 port multi-PHY. The PHY-ID of
each cell is identified using in-band
addressing.
Any-PHY receive slave appears as a
single device. The PHY-ID of each cell
is identified using in-band addressing.
UTOPIA L2 transmit and receive slave
appears as a 31-port multi-PHY.
UTOPIA L2 receive slave can also
appear as a single port with the logical
port provided as a prepend.
TC Layer
(RTTC32)
INSBI
EXSBI
De-
Framer
(SDDF32)
TC Layer
(TTTC32)
Rx IMA
Protocol
Processor
(RIPP)
IDCC
32-chan
x 7 cell
FIFO
(MCFD)
32-chan
x
3 cell
FIFO
Tx IMA Processor
(TIMA)
Any-PHY/
UTOPIA
Tx Slave
(TXAPS)
Any-PHY/
UTOPIA
Rx Slave
(RXAPS)
31
chan
4 cell
FIFO
MicroProcess I/F
JTAG
IDCC
DLL
32-chan
x 2 cell
FIFO
Null
Framer
(SDFR32)
Tx Slave
ATM I/F
Rx Slave
ATM I/F
RCLK
RPA
SBI Drop Bus I/F
DC1FP
DDATA[7:0]
32 Clk/Data
TSCLK[31:0]
TSDATA[31:0]
CTSCLK
RCAS
TCAS
Internal Bus
Rx IMA
Data Processor
(RDAT)
Cell Writer Cell Reader
Memory Interface
(MEMI)
C
C
C
C
C
C
C
C
RCSB
RSOP
RSX
RDAT[15:0]
RPRTY
RADR[4:0]
TCLK
TCSB
TSOP
TSX
TDAT[15:0]
TADR[10:0]
D
A
A
W
R
C
I
T
T
T
T
T
S
R
O
DV5
DPL
ADAAC1FP
APL
AJUST_AV5
AACTIVE
ADETECT
SBI Add Bus I/F
32 Clk/Data
RSCLK[31:0]
RSDATA[31:0]
R
BLOCK DIAGRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PM7344 制造商:PMC 制造商全稱:PMC 功能描述:SATURN QUAD T1/E1 MULTI-PHY USER NETWORK INTERFACE DEVICE
PM7344-RI 制造商:PMC-Sierra 功能描述:7344-RI