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PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
129
SarDiagWrModeEn
When enabled, the SAR receive staging buffer will be used as a port to write
data directly to the cell buffer (SDRAM). Receiving of normal cells into the
traffic stream is no longer possible while this parameter is enabled. This bit
should only be set when SarRxEmptyStatus = 1 in the low interrupt status
register.
SarDiagRdModeLock
Read only. Indicates that the SAR is ready to perform a diagnostic reads. A
lock will only occur when SarDiagRdModeEn = 1, and all non-diagnostic cells
remaining in the class 3 Tx staging buffers have been read by the
microprocessor.
SarDiagRdModeEn
When enabled, normal loading of cells into all 4 classes of the SAR Tx
staging buffers are withheld. A cell that is in the process of being loaded into
a Tx staging buffer when this bit is set will be allowed to complete.
SarDiagRdBusy
Setting this register to one will initiate a diagnostic read from the cell buffer
(SDRAM). When the command is complete, this bit will be cleared to zero.
This bit should not be set to one until SarDiagRdModeEn = 1,
SarDiagRdModeLock = 1, and SarTxRdyStatus = 0.
12.6 Queue Engine
Register 0x700: Queue Context Configuration
Bit
Type
Function
Default
31
R/W
QEngEn
0
30
R
QBusy
0
29
R/W
QSglStep
0
28:27
Unused
0
26
R/W
QRxTxArbSel
0
25
Unused
0
24
R/W
QNumVCSel
0
23:16
R/W
QCellStartAdr[7:
0]
0
15:8
R/W
QLClassStartAdr
0