![](http://datasheet.mmic.net.cn/330000/PM7329-BI_datasheet_16444382/PM7329-BI_106.png)
PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
92
Figure 28
- 16 MB – 256k Cells
CKE
CLK
Addr/Ctrl
DQM[1:0]
DQ[15:0]
4 x 4k x 256 x 16
1
1
CKE
CLK
Addr/Ctrl
DQM[1:0]
DQ[15:0]
4 x 4k x 256 x 16
clock source
SYSCLK
CBCSB
CBRASB
CBCASB
CBWEB
CBBS[1:0]
CBA[11:0]
CBDQM[0]
CBDQ[15:0]
CBDQM[1]
CBDQ[31:16]
to SSRAM
There are three processes, arbitrated by the SDRAM arbiter, that access the cell
buffer SDRAM:
1. The queue engine, for reading and writing cells. The granularity of access by
the queue engine is a concatenated 1 cell write - 1 cell read. Either the write
or the read may not be performed, depending on the queue engine’s
requirements;
2. The microprocessor interface, for diagnostic reading or writing of 64 bytes of
data. This data is aligned with the cell data. See the Operations section for a
description of the data format;
3. The refresh controller, which has a programmable refresh rate.
The SDRAM interface will perform the initialization sequence for the SDRAM.
This sequence is triggered by the SDRAM enable bit CBEn. The sequence will
program the SDRAM with a CAS latency of 3, sequential access, write burst
mode, and a burst length of 8. Application should ensure that sufficient time is
provided between SDRAM power-up and when this enable bit is set.