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PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
21
Pin Name
Type
Pin
No.
Function
LRSOP
Input
J2
Loop Receive Start of Packet .
LRSOP marks the
start of the cell on the LRDAT[15:0] bus. When
LRSOP is high, the first data word of the cell is
present on the LRDAT[15:0] stream. If the selected
device is an Any-PHY device, the LRSOP cycle will
be preceded by the LRSX cycle marking the Any-
PHY port address transfer cycle.
LRSOP considered valid only when the LRENB
signal is low. LRSOP becomes high impedance
upon sampling LRENB high or if no physical layer
device was selected for transfer.
LRSOP is sampled on the rising edge of LRCLK.
LRDAT[0]
..
LRDAT[15]
Input
J1
K2
L3
K1
L2
M4
L1
M3
M2
M1
N3
N2
P2
P3
P4
R1
Loop Receive Data.
LRDAT[15:0] carries the
transfer block words that have been read from the
physical layer device to the S/UNI-APEX-1K800
internal cell buffers.
LRDAT bus is considered valid only when the
LRENB signal was low N cycles previous. LRDAT is
expected to become high impedance N LRCLK
cycles after sampling LRENB high or upon
completion of a data block transfer. If the PHY
device is a UTOPIA device, N=1. If the PHY device
is an Any-PHY device, N=2.
All 16 bits are used in 16-bit mode. In 8 bit mode,
LRDAT[15:8] should either be tied high or low, as
only the first 8 bits LTDAT[7:0] are valid.
LRDAT[15:0] is sampled on the rising edge of
LRCLK.