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PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
45
Pin Name
Type
Pin
No.
Function
SYSCLK
Input
B12
System Clock.
This clock is the master clock for the
S/UNI-APEX-1K800 device. All non-Any-PHY or
microprocessor interface related internal
synchronous logic is timed to this signal. SYSCLK
must cycle at a 80 MHz or lower instantaneous rate.
External SSRAM and SDRAM devices share this
clock and must have clocks aligned within 0.2ns
skew of the clock seen by the S/UNI-APEX-1K800
device.
This clock must be stable prior to deasserting RSTB
0->1.
NC
AB4
AC5
AB23
E23
D22
D5
E24
No Connect.
These balls are not connected to the
die.
9.9 JTAG & Scan Interface (7 Signals)
Pin Name
Type
Pin
No.
Function
TCK
Input
AD1
Test Clock.
This signal provides timing for test
operations that are carried out using the IEEE
P1149.1 test access port.
TMS
Input
AC2
Test Mode Select.
This signal controls the test
operations that are carried out using the IEEE
P1149.1 test access port. TMS is sampled on the
rising edge of TCK. TMS has an integral pull-up
resistor.
TDI
Input
AB3
Test Data Input.
This signal carries test data into
the S/UNI-APEX-1K800 via the IEEE P1149.1 test
access port. TDI is sampled on the rising edge of
TCK. TDI has an integral pull-up resistor.