參數(shù)資料
型號: PLB2224
英文描述: 24+2G Switch On a Chip with Embedded Memory
中文描述: 24第二代開關(guān)與嵌入式內(nèi)存芯片
文件頁數(shù): 78/219頁
文件大?。?/td> 2975K
代理商: PLB2224
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁當(dāng)前第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁
GREEN
PLB 2224
Operational Description
Data Sheet
78
2002-06-03
5.4
Packet Classification
The packet classification and filtering feature enables the PLB 2224 to identify patterns
within the first 64 B of packet data and take a specific action if a match is found. Packet
filtering allows identification of packets such as protocol type (i.e., an IP packet), TOS
values within a certain range of the IP packet, and IGMP control packet. Once a packet
is classified, one of the following actions can be taken:
Increment a dedicated counter for management purposes,
Forward the packet to a port designated for forwarding such packets. Typically the
forwarding port is a CPU port, but it could also be some other port,
Discard the packet, i.e., do not forward it to the normal destination port(s),
Monitor the packet, i.e., forward it to the monitoring port,
Assign HIGH priority to the packet.
The data pattern(s) used for identification and handling actions are configured globally
and are shared by all ports on the PLB 2224.
Figure 15
shows how packet filtering is
accomplished.
Several registers are used to implement packet classification and filtering. They are
described in
Chapter 7
. These configuration registers are mapped into the CPU address
space and can be loaded using the CPU interface.
The packet identification is done with the help of four groups of pattern registers. The
groups are identified as Group #0 through #3, and pattern sets within a group are
identified as pattern #0 through #3. Out of the 4 groups, pattern registers in group #0 and
#1 are user configurable, while in group #2 and #3 they are hard coded to identify IP
protocol packets in 802.3 SNAP and Ethernet II frame formats respectively. Groups #0
and #1 each consist of 4 pattern sets. Each set has a 16-bit pattern value, a 16-bit mask,
5-bit offset, and a flag for the type of comparison (LE or EQ).
When a packet is received by a port on the PLB 2224, the two bytes with the starting half-
word (==2-bytes) address of offset[5:1] within the packet are compared with the data
stored in pattern[15:0], and a match signal is generated when the results of the
comparison are true. In doing the comparison, the pattern[15:0] is qualified by the
corresponding mask[15:0]. A 1 at any position in the mask implies that the corresponding
bit in the Ethernet packet and the pattern register are not being compared (i.e., they are
considered matched).
The first pattern set (i.e., pattern set #0) in each group can be programmed to generate
a match when the packet data is less than or equal to (LE) the pattern data. Setting the
corresponding comp_le0 bit to a 1 does this. The other three pattern sets can only check
if the Ethernet packet data is equal to the pattern. Thus, groups #0 and #1 generate four
match signals each, called match0 through match3
1
2
Number of multicast packets
Number of packets dropped
相關(guān)PDF資料
PDF描述
PLBYTEBLASTERCABLE 60MHz, Rail-to-Rail Output, 1.9nV/rtHz, 1.2mA Op Amp Family; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C
PLC01-6 60MHz, Rail-to-Rail Output, 1.9nV/rtHz, 1.2mA Op Amp Family; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C
PLC03-6 500mA, 200MHz xDSL Line Driver in 16-Lead SSOP Package; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +85°C
LCO3-6 Direct ProTek Replacement:PLC03-6
PLC16V8H35N Dual 500mA, Differential xDSL Line Driver in 28-Lead TSSOP Package; Package: TSSOP; No of Pins: 28; Temperature Range: 0°C to +70°C
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PLB2224EV1.3 制造商:Rochester Electronics LLC 功能描述:
PLB24 制造商:Pentair Technical Products / Hoffman 功能描述:Lifting Bars (2) , 2400mm wide, Steel
P-LB24 制造商:Pentair Technical Products / Hoffman 功能描述:Lifting Bars (2)
PLB2800 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Configurable Ethernet Switch-on-a-Chip
PLB2S-C 功能描述:電纜束帶 Double Loop Tie 7.6"L (193mm) Std RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Cable Tie Mounts 類型:Adhesive 顏色:Black 材料:Acrylonitrile Butadiene Styrene (ABS) 長度:19 mm 寬度:19 mm 抗拉強(qiáng)度: