參數(shù)資料
型號(hào)： PLB2224
英文描述： 24+2G Switch On a Chip with Embedded Memory
中文描述： 24第二代開(kāi)關(guān)與嵌入式內(nèi)存芯片
文件頁(yè)數(shù)： 32/219頁(yè)
文件大?。?/td> 2975K
代理商： PLB2224
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GREEN
PLB 2224
Functional Description
Data Sheet
32
2002-06-03
is used with the PHY devices (called serializer/deserializer or SERDES devices) that do
not contain the PCS functionality – for example Vitesse’s VSC7123 and HP’s
HDMP1636. For each gigabit port, the corresponding configuration bit sel_Gb is set to 1
to choose 1 Gbit/s speed, and bit
TBI / GMII
bit is set to 1 for TBI and the GMII bit is set
to select between GMII mode of operation or MII mode of operation. See Configuration
Register. The gigabit ports are full duplex only for 1000Mbit/s and can be used for Half
Duplex in 10/100 Mbit/s mode.
Connecting to external 100 Mbit/s PHY devices
The gigabit Ethernet ports can also connect to 100 Mbit/s PHY devices supporting the
MII . For example, the two gigabit ports can be used for 100FX uplinks. For each gigabit
port, the corresponding configuration bit sel1000 bit is set to 0 to choose 100 Mbit/s
speed with MII in the
Table 109 "G_Mode Register" on Page 193
. The gigabit ports
when used as 100 Mbit/s ports can operate in full duplex mode or half duplex.
Connecting PLB 2224s back-to-back
The GMII on the PLB 2224 can also be used to connect two PLB 2224 devices on the
same board, effectively acting as a high capacity trunk between them. Connecting two
PLB 2224s back-to-back in this fashion makes it possible to design a fixed configuration
or stackable 48-port 10/100 switch that is rack mountable.
Note that this configuration
does not require gigabit PHY devices
.
3.2.1.3
MDIO Interface
The MDIO Serial Interface defined in the MII specification is used for communicating
with the PHY device(s). Using this interface, PLB 2224 can access the internal
registers of the PHY devices.
Auto-Negotiation
PLB 2224 supports auto-negotiation on the 10/100 ports. Autonegotaiation on the
Gports is supported when the GMII mode of operation is selected. Using the MDIO
interface the ports can negotiate the link parameters - speed, duplex mode and
pause_enable (i.e. full-duplex control) and pause_augment (for gigbit speed only).
This allows the switch to neogotiate the status and capabilities of the PHY device and
configure itself appropriately.
For SMII, the link information can be obtained by reading the status information
continuously coming over the SMII or by accessing the PHY registers using the MDIO
interface. See
use_mdio_mode
bit in
“Chip Configuration Register” on Page 141
section. For the gigabit ports, the auto-negotiation is performed using the MDIO
interface when the GMII or MII option is selected.
Using the MDIO interface, the CPU can access the PHY device registers and override
the auto-negotiated settings if desired. e_hw_mode bit in
“Switch Configuration
Register” on Page 145
must be cleared to 0 in order to disable auto-negotiation.
For the MDIO interface, the Ethernet (PHY) port addresses are mapped into MDIO
address space as follows:
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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PLB24 制造商:Pentair Technical Products / Hoffman 功能描述:Lifting Bars (2) , 2400mm wide, Steel
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